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PCIe link up drop problem

xing wang
Intellectual 340 points

Steven Ji, you probably remember my old problems.

It has been a very long time that I've been stuck in this.

The situation is as follows:

1. my board FPGA connecting 6678.

 high chance of link up. but it will drop once link up, the ltssm field will drop to 0. So, no further things i can do on it.

2. two 6678EVM with BoC board 

 same  phenomenon(I　only change the EP RC configuration in the pcie example from MCSDK　and add some print of debug0)

I'm quite confused about this, is there any key point I should pay attention to when i connect the two evm with BoC?

or is it just my configuration problem？

  • 0
    TI__Genius 12065 points

    Xing,

    Maybe we can start with the two 6678 case.

    You are using the separate clock on each board as the PCIe reference clock, is it correct?

    Could you check if the LOCK bit =1 in PCIE_SERDES_STS (0x0262015c) indicates the PCIe PLL has been locked all the time? What about the LOCK bit when the link is down?

    If you are using exactly the PDK/MCSDK PCIe examples on both of the EVMs (one RC and one EP), the configuration should be fine. The "printf of debug0" only reads the debug0 register (no write or read of other registers), is it correct?