The internally gated interface clock of AM335x GPIO.

Biser-san,

Thanks for your comment.I refered section 25.2.2.
But, there is no explanation about the definition of "the internally gated interface clock".

What is it?
Is my thinking NOT correct? : "the internally gated interface clock" is function clock

Best regards, RY

Biser-san,

Thank you so much for your reply.
I am sorry. I have not been able to understand enough what you want to say.
I read the section 25.3.2.2 and Table 25-3.

On 25.3.2.2: All channels are also gated using a ‘one out of N’ scheme. N can take the values 1, 2, 4 or 8. The interface clock is enabled for this logic one cycle every N cycles. When N is equal to 1, there is no gating and this logic is free running on the interface clock. When N is between 2 to 8, this logic is running at the equivalent frequency of interface clock frequency divided by N.

You would like to say this is the "internally gated interface clock"?
If yes, it is same of my thinking.
Also, I think it is set by GPIO_CTRL register and it is named functional clock.
Is that right?

Best regards, RY