Ethercat Ethernet and MDIO

Stefano Bisi

Other Parts Discussed in Thread: CDCE913

Goodmorning,

we are working on a custom board which should work as EtherCAT slave in some application and as ieee 802.3 Ethernet 10/100 in others application or both.

I've read that the PRU code implementing standard Ethernet is under development but we can't wait for it .

so we found a pin mux arrangement that seem could work in both mode but we have two question related to EtherCAT implementation on PRU.

What happen if we put PRUSS1_MII1 pins in Z while using PRU EtherCAT code ?

What happen on MDIO bus if i connect both MDIO port and MDIO_PRUSS1 port to my PHYs ? Like ET1100, does PRUSS take exclusive control of MDIO bus ?

Thank in advance

Stefano

over 12 years ago

0 Srik Gurrapu over 12 years ago

TI__Expert 3353 points

Hello Stefano,

Yes, that's possible. In fact, we are working on a rev of ICE EVM to implement this MUX to switch the ICE EVM Ethernet ports between PRU or the Gibabit switch. We've early protos of ICE2 EVM and can share with you the current schematics.

Pl contact me at gurrapu@ti.com and I can send you these schematics that you can use for your system.

Thanks,

-Srik

0 Stefano Bisi over 12 years ago in reply to Srik Gurrapu

Intellectual 460 points

Srik goodmorning,

thanks for the schematics, I find very interesting the use of CDCE913 to generate the clocks. But I have a doubt about the voltage level of AM335x_OSC0_IN.

CDCE913 outputs are 3.3 V level voltage but OSC0_IN is in VDDS_OSC power domain ( 1.8 V ) . What happen if i apply a 3.3 V clock to XTALIN pin ?

Thank in advance

Stefano

0 ddomke over 12 years ago in reply to Stefano Bisi

TI__Intellectual 2150 points

The AM335x_OSC0 is actually using a crystal Y3 and not the output of the CDCE913. R144 is not populated on the board.

0 Stefano Bisi over 12 years ago in reply to ddomke

Intellectual 460 points

Yes, of course, I saw the crystal and the DNI resistor but my question is

" In which way a 3.3 V clock can feed a 1.8 V input ?"

At first sight it would seem an error.

Regards

Stefano

Processors

Processors forum

Ethercat Ethernet and MDIO