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PCIe bar Setting Config / Window Size

larry bernstein
Intellectual 280 points

Hello,   ......We are have a C6655 as an EP processor  and will be using PCIe as the booting mode ( there is  no IBL I2C device) .  Can the RC device set the window size of  BAR 1-4  on C6655  as described in section 2.7.3.1  of the PCIe User Guide  SPRUGS6C . We would like to over-ride the PCIe window size determined by the 4 boot pins as shown in Figure 3-15 of the Bootloader User Guide  SPRUGYB.   We have attempted to do this on the  TI EVM  PCB  and have been unsuccesful.    I see similar questions regarding BAR window size  but not this one specifically.  Thank you for any assistance in this matter.

  • 0
    TI__Genius 12065 points

    Larry,

    The BAR window size is determined by the BAR Mask registers. Section 2.7.3.1 specifies that "It is important to not attempt modification of BAR Mask registers from serial link side

    as unpredictable behavior may occur and the system would become unusable."

    So it is not recommended to change the BAR mask registers (window size) by the external RC/host device (maybe not accessible by the external device, as you observed).

    The BAR mask registers should be accessible by the local device via internal bus. So if you need to change the window size, it might be better to update the boot code (may add in IBL) to let EP change the window size by itself before RC configures the BAR register (not BAR mask register) of EP.

  • 0 in reply to Steven Ji
    Intellectual 300 points

    Steven,

    We are trying to configure the window sizes using the EVM Dip Switches (SW3-7, SW3-8, SW5-1, SW5-2) but several configuration setting options cause the link not to come up / connect from our EVM EP to the RC.  The combinations that fail are when Switch 3 - pin 8 is set to 1.

    Is the IBL causing these window size options to be invalid and causing the link issues or something else ????

    We need to configure our EVM window sizes to the 4,128,256,256 window size option and cannot get this to work.

     

    Thanks 

     

  • 0 in reply to Joseph Furno
    TI__Guru* 95265 points

    SID814,

    I would like to know what EVM card you are using, looks like 6657? Then is it beta board (TMDXEVM6657L(E)) or production board (TMDSEVM6657LS)?

    In beta baord, when you select PCIE boot mode, the FPGA will direct the boot from I2C, where the IBL configured the BAR size, what you done in Switch 3-7/8, Switch 5-1/2 has no effort.

    In the production board, it will boot directly from RBL (no FPGA redirect to IBL). So the Switch 3-7/8, Switch 5-1/2 are effective. As you are requesting the maximum (4,128,256,256) window size, what is your RC? Is it a Linux machine? How many memory it has? I knew in many cases, the RC doesn't have sufficient memory and PCIE is not link up. You can try a different machine with more memory installed or change the 6657 EVM switch to request smaller memory to see if works.

    Regards, Eric 

  • 0 in reply to lding
    Intellectual 280 points

    Hi Eric,  I  work with SID814  and will answer your questions and provide more info.. The EVM is for a 6657 as you expected .. The EVM revision ID silkscreen   we are using is  PCA  = Rev 18-00132-01 and PCB Rev = 17-00132-01 . Which according to section 2.3 of SPRUHG7 ( EVM Reference Manual)  is a "Proto + Alpha Build ( Initial engineering samples)..  The behavior we are getting does not match either of the two behaviors you describe.. The BAR windows size does change in several cases  as expected  (  Table 2-12 of C6655/57 data sheet) when Switch 3 7/8 and Switch 5 1/2  settings change.  What we are finding is whenever   (Bootmode Pin 6  / GPIO 7)   DIPSW 3-8 is open "1",  Barcfg = 0bxx1x, the PCIe link does not work ( We can see the PCIe Bus Analyzer cannot lock to EP DSP)..  The Barcfg = 1011  is the option  we need to get  4/128/256/256 Bar Windows since the earlier response on this thread was that the Bar window  size cannot be changed from the serial side ( by the RC)   Note that we have reprogrammed the IBL program  as TI recommended  to  disable the PCIe workaround function of the IBL  refer to this thread    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/234593/838636.aspx#838636    We do have an EVM board  PCA  = Rev 18-00132-02 and PCB Rev = 17-00132-02  which corresponds to  " Beta Build/ Production Build" but we had problems updating the IBL to  disable the PCIe workaround function of the OTS IBL. Thus we have not been using it.      We are using a FPGA as the RC and the total window size we are using is not expected to be an issue.   We would like to understand if there is anything about EVM/IBL which explain behavior we are seeing  ( i so is there a workaround)  and  most importantly to be confident when our product PCB arrives in about a week that we will be able to set  Barcfg to  0b1011  and get 4/128/256/256 Bar Windows . Thanks  Larry

  • 0 in reply to larry bernstein
    TI__Guru* 95265 points

    Larry,

    Can you clarify a bit "....C6655 as an EP processor  and will be using PCIe as the booting mode ( there is  no IBL I2C device)" at the beginning of this thread? I assume you are using an alpha version 6657 EVM with IBL reprogramed to disable PCIE_WORKAROUND for the discussion..

    In this case, PCIE is configured by RBL and if both RC (your FPGA) and EP use a 100 Mhz clock (not SS clock), it worked from some BAR settings from switch. From your finding, "whenever (Bootmode Pin 6  / GPIO 7)   DIPSW 3-8 is open "1",  Barcfg = 0bxx1x, the PCIe link does not work." Do you know if this pin selection is correctly reflected in DEVSTAT register (0x2620020)? The RBL code uses this barcfg bits to configure the BAR mask. The issue looks the BAR mask configured by RBL can't work with your RC. Are you able to read back the BAR mask in this case according to PCIE user guide 2.7.3.1 BAR Mask Registers? Sorry, I don't have the set-up for a try.

    Another thing is if you can reprogram the IBL of beta board you have, you can double check if this problem is caused by the alpha board. What issue you are facing to update the IBL? It is same procedure as the alpha board.

    Regards, Eric  

     

  • 0 in reply to lding
    Intellectual 280 points

    Eric, Thanks for reply.  We did try  a similar testing on beta version of the TI EVM  PCB but ran into other issues and decided to wait  another week to test  BAR size  (Barcfg = 0b1011) when our product  PCB arrived which has boot pins wired directly to pull-up /pull-down resistors.   Fast forward to today..   C6655 is working as TI documentation  indicates..  Barcfg = 0b1011 results in Window sizes  4//128/256/226 MBs for Bars 1-4 respectively.  Of course, DEVSTAT  resgister correctly indicates state of boot configuration pins.  Larry