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the question about CPSW_PRI register

Hi TI Team,

    in the AM335x specification, there are registers of P0_TX_PRI_MAP, P0_CPDMA_TX_PRI_MAP,

    P0_CPDMA_RX_CH_MAP and P0_RX_DSCP_PRI_MAP0,

    but we don't understand these registers explanation.

    where are these register used to?

    in the CPSW_ALE register, there are six PROTCTLx registers.

    these registers explanation are ADDRESS LOOKUP ENGINE PORT x CONTROL REGISTER,

   but we know there are only three ports with CPSW.

   why are there six PROTCTLx registers?

  • These priority registers give the customer the ability to map certain ports and/or packets to different priorities in the switch fabric.  Normally this is used when customers have special use cases and/or are using priority tagged packets on their network.

     

    The priority functionality is explained a bit better in sections 14.3.2.8, 14.3.2.9, and 14.3.2.10 in the TRM.  There are other references to packet priority throught-out the TRM but the above sections are the best place to start to get a basic understanding of how it works.