A　C6678 IPC interrupt problem

Jason Gao

#include <stdio.h>
#include <string.h>
#include <c6x.h>
#include <ti/csl/cslr_device.h>
#include <ti/csl/csl_edma3.h>
#include <ti/csl/csl_intc.h>
#include <ti/csl/csl_intcAux.h>
#include <ti/csl/cslr_device.h>
#include "my.h"
#define TPCC_BASEADDR(n)			(0x02700000 + n * 0x20000)
#define IPR(n)						*(volatile int*)(TPCC_BASEADDR(n) + 0x1068)

#define		INTC_BASEADDR(n)				(0x02600000 + n * 0x4000)
#define		STATUS_SET_INDEX_REG(n)			*(volatile unsigned int*)(INTC_BASEADDR(n) + 0x020)

void Generate_IPC_Interrup(int coreNum, int info);
int IPC_Interrup_Process();
void IPCInterruptHandler();
void main()
{
	int i = 0;
	intc_init();
	IntcBind(CSL_GEM_IPC_LOCAL,CSL_INTC_VECTID_6, IPCInterruptHandler);
	if(DNUM == 1)
	{
		for(i = 0; i < 8; i++)
		{
			Generate_IPC_Interrup(i,i);
		}
	}
	while(1);
}

/*
 * ����˵�����ú���ʵ�ָ�8�����е�����һ���˷���һ��IPC�ж�
 * ����˵����int coreNum���˱��
 * 			int info��	�������˷��͵���Ϣ������Ϣ����Ϊ0bit-27bit,����ÿһλ��λ����������ʾһ����Ϣ�������Ϣ�ĸ�ʽ�Զ���
 * ��ע��	�ú�����ͬһʱ��ֻ�ܸ�һ���˲���һ��ͬ���¼�
 */
void Generate_IPC_Interrup(int coreNum, int info)
{
	hIpc->IPCGR[coreNum] |= (info << 4);
	hIpc->IPCGR[coreNum] |= 0x1;
	return;
}

/*
 * ����˵�����ú�������IPC�жϷ�������У�����IPC�жϷ��������ʱ�����øú��������ط��ͷ����ݵ���Ϣ
 * ����˵���� ��
 */
int IPC_Interrup_Process()
{
	int info;
	info = hIpc->IPCGR[DNUM] & 0xFFFFFFF0;
	hIpc->IPCAR[DNUM] = info;
	return (info >> 4);
}

void IPCInterruptHandler()
{
	int info;
	info = IPC_Interrup_Process();
	printf("info = %d\n",info);
}

Hi all,

I meet a problem with the IPC interrupt, i writed IPCGRx to set up a interrupt to corex.

when i set a specific vector id except for the 4th vector id, the target core will enter twice interrupt ,

i have check the IFR register , the bit Corresponds to the 4th vector id will always be set up regardless of the specific vector id i used after i writed the IPCGRx of the target core , i don't know why ? can anyone help?

the code is pasted:

Fullscreen 2072.main.txt Download

#include <stdio.h> #include <string.h> #include <c6x.h> #include <ti/csl/cslr_device.h> #include <ti/csl/csl_edma3.h> #include <ti/csl/csl_intc.h> #include <ti/csl/csl_intcAux.h> #include <ti/csl/cslr_device.h> #include "my.h" #define TPCC_BASEADDR(n) (0x02700000 + n * 0x20000) #define IPR(n) *(volatile int*)(TPCC_BASEADDR(n) + 0x1068) #define INTC_BASEADDR(n) (0x02600000 + n * 0x4000) #define STATUS_SET_INDEX_REG(n) *(volatile unsigned int*)(INTC_BASEADDR(n) + 0x020) void Generate_IPC_Interrup(int coreNum, int info); int IPC_Interrup_Process(); void IPCInterruptHandler(); void main() { int i = 0; intc_init(); IntcBind(CSL_GEM_IPC_LOCAL,CSL_INTC_VECTID_6, IPCInterruptHandler); if(DNUM == 1) { for(i = 0; i < 8; i++) { Generate_IPC_Interrup(i,i); } } while(1); } /* * ��˵��ú��ʵ�ָ�8��е��һ��˷��һ��IPC�ж� * ��˵��int coreNum��˱�� * int info�� ˷��͵��Ϣ��Ϣ��Ϊ0bit-27bit,��ÿһλ��λ��ʾһ��Ϣ��Ϣ�ĸ�ʽ�Զ�� * ��ע�� ú��ͬһʱ��ֻ�ܸ�һ��˲��һ��ͬ��¼� */ void Generate_IPC_Interrup(int coreNum, int info) { hIpc->IPCGR[coreNum] |= (info << 4); hIpc->IPCGR[coreNum] |= 0x1; return; } /* * ��˵��ú��IPC�жϷ��У��IPC�жϷ��ʱ��øú��ط��ͷ��ݵ��Ϣ * ��˵�� */ int IPC_Interrup_Process() { int info; info = hIpc->IPCGR[DNUM] & 0xFFFFFFF0; hIpc->IPCAR[DNUM] = info; return (info >> 4); } void IPCInterruptHandler() { int info; info = IPC_Interrup_Process(); printf("info = %d\n",info); }

Thanks ,

Jason Gao.

over 12 years ago

0 Steven Ji over 12 years ago

TI__Genius 12065 points

Jason,

Please take a look at the INTMUX1 register (0x01800104) in the CorePac INTC to see if the source event has been programmed to the INTSEL4 (vector ID 4) as well.

If so, the same source event will trigger both the INTn (the one you desired) and INT4.

If not, please provide the source code such as "IntcBind()" "my.h" that we could reproduce the issue.

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A　C6678 IPC interrupt problem

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A C6678 IPC interrupt problem

A　C6678 IPC interrupt problem