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Interfacing GPMC with a SMSC LAN9220 ethernet chip

Other Parts Discussed in Thread: DM3730, SYSCONFIG

Hello,

I am in the process of getting a CompuLab CM-T3730 board (contains DM3730 SoC) to run QNX as its OS. This board has an SMSC LAN9220 ethernet chip connected to the SoC via GPMC chip-select 5. CompuLab provides a working Linux OS for their board, and therefore we have been able to review this code and also boot the OS while dumping out register values in order to view what is necessary to get the GPMC talking with the LAN9220. However, when trying to read LAN9220 registers, we get 0xFFFFFFFF values, indicating something is not properly set-up between the GPMC and LAN9220.

As part of our boot-up, we have set the GPMC_* and CONTROL_PADCONF_GPMC* registers according to what we believe to be correct, which are in-line with the Linux boot-up. Are there any additional configurations we are required to do in order to get the chip running?

Also, can anyone suggest how we can go about debugging this problem? Are there any tools which can assist us in getting this system properly configured?

Thanks,
David

  • Hi David,

    I could try to support you about the issue only for the dm3730 side. You can read description of the Pad configuration register CONTROL_PADCONF_X in the Technical reference manual - section 13.6.3.2 (page 2556) at the link:

    http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf

    You can use for debugging (reading and writing) values of the registers the readmem tool which is attached below.

    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/537/7534.readmem

    BR

    Tsvetolin Shulev

  • Hi Tsvetolin,


    Thanks for your response. How can I use the readmem tool?

    I already have a dump of our GPMC_* and CONTROL_PADCONF_GPMC* registers, which are identical to our working linux solution; see below. Are there any other registers which might be useful to look at?


    [CONTROL_PADCONF_GPMC_A1]: 0x0018
    [CONTROL_PADCONF_GPMC_A2]: 0x0018
    [CONTROL_PADCONF_GPMC_A3]: 0x0018
    [CONTROL_PADCONF_GPMC_A4]: 0x0018
    [CONTROL_PADCONF_GPMC_A5]: 0x0018
    [CONTROL_PADCONF_GPMC_A6]: 0x0018
    [CONTROL_PADCONF_GPMC_A7]: 0x0018
    [CONTROL_PADCONF_GPMC_A8]: 0x0018
    [CONTROL_PADCONF_GPMC_A9]: 0x0018
    [CONTROL_PADCONF_GPMC_A10]: 0x0018
    [CONTROL_PADCONF_GPMC_D0]: 0x0118
    [CONTROL_PADCONF_GPMC_D1]: 0x0118
    [CONTROL_PADCONF_GPMC_D2]: 0x0118
    [CONTROL_PADCONF_GPMC_D3]: 0x0118
    [CONTROL_PADCONF_GPMC_D4]: 0x0118
    [CONTROL_PADCONF_GPMC_D5]: 0x0118
    [CONTROL_PADCONF_GPMC_D6]: 0x0118
    [CONTROL_PADCONF_GPMC_D7]: 0x0118
    [CONTROL_PADCONF_GPMC_D8]: 0x0118
    [CONTROL_PADCONF_GPMC_D9]: 0x0118
    [CONTROL_PADCONF_GPMC_D10]: 0x0118
    [CONTROL_PADCONF_GPMC_D11]: 0x0118
    [CONTROL_PADCONF_GPMC_D12]: 0x0118
    [CONTROL_PADCONF_GPMC_D13]: 0x0118
    [CONTROL_PADCONF_GPMC_D14]: 0x0118
    [CONTROL_PADCONF_GPMC_D15]: 0x0118
    [CONTROL_PADCONF_GPMC_NCS0]: 0x0118
    [CONTROL_PADCONF_GPMC_NCS1]: 0x0100
    [CONTROL_PADCONF_GPMC_NCS2]: 0x011f
    [CONTROL_PADCONF_GPMC_NCS3]: 0x0004
    [CONTROL_PADCONF_GPMC_NCS4]: 0x0118
    [CONTROL_PADCONF_GPMC_NCS5]: 0x0000
    [CONTROL_PADCONF_GPMC_NCS6]: 0x011c
    [CONTROL_PADCONF_GPMC_NCS7]: 0x0004
    [CONTROL_PADCONF_GPMC_CLK]: 0x0104
    [CONTROL_PADCONF_GPMC_NADV_ALE]: 0x0f00
    [CONTROL_PADCONF_GPMC_NOE]: 0x0f00
    [CONTROL_PADCONF_GPMC_NWE]: 0x0f00
    [CONTROL_PADCONF_GPMC_NBE0_CLE]: 0x0018
    [CONTROL_PADCONF_GPMC_NBE1]: 0x0004
    [CONTROL_PADCONF_GPMC_NWP]: 0x0100
    [CONTROL_PADCONF_GPMC_WAIT0]: 0x0118
    [CONTROL_PADCONF_GPMC_WAIT1]: 0x0118
    [CONTROL_PADCONF_GPMC_WAIT2]: 0x011f
    [CONTROL_PADCONF_GPMC_WAIT3]: 0x0104

    [GPMC_REVISION]: 0x00000050
    [GPMC_SYSCONFIG]: 0x00000011
    [GPMC_SYSSTATUS]: 0x00000001
    [GPMC_IRQSTATUS]: 0x00000000
    [GPMC_IRQENABLE]: 0x00000000
    [GPMC_TIMEOUT_CONTROL]: 0x00000000
    [GPMC_ERR_ADDRESS]: 0x00000000
    [GPMC_ERR_TYPE]: 0x00000000
    [GPMC_CONFIG]: 0x00000010
    [GPMC_STATUS]: 0x00000301
    [GPMC_PREFETCH_CONFIG1]: 0x00004000
    [GPMC_PREFETCH_CONFIG2]: 0x00000000
    [GPMC_PREFETCH_CONTROL]: 0x00000000
    [GPMC_PREFETCH_STATUS]: 0x00000000
    [GPMC_ECC_CONFIG]: 0x00001030
    [GPMC_ECC_CONTROL]: 0x00000000
    [GPMC_ECC_SIZE_CONFIG]: 0x3fcff000
    [GPMC_BCH_SWDATA]: 0x00000000
    GPMC CS 0 Registers
    [GPMC_CONFIG1]: 0x00001800
    [GPMC_CONFIG2]: 0x00141400
    [GPMC_CONFIG3]: 0x00141400
    [GPMC_CONFIG4]: 0x0f010f01
    [GPMC_CONFIG5]: 0x010c1414
    [GPMC_CONFIG6]: 0x1f0f0a80
    [GPMC_CONFIG7]: 0x00000000
    GPMC CS 1 Registers
    [GPMC_CONFIG1]: 0x00001000
    [GPMC_CONFIG2]: 0x00101001
    [GPMC_CONFIG3]: 0x00020201
    [GPMC_CONFIG4]: 0x10031003
    [GPMC_CONFIG5]: 0x010f1111
    [GPMC_CONFIG6]: 0x8f030000
    [GPMC_CONFIG7]: 0x00000f00
    GPMC CS 2 Registers
    [GPMC_CONFIG1]: 0x00001000
    [GPMC_CONFIG2]: 0x00101001
    [GPMC_CONFIG3]: 0x00020201
    [GPMC_CONFIG4]: 0x10031003
    [GPMC_CONFIG5]: 0x010f1111
    [GPMC_CONFIG6]: 0x8f030000
    [GPMC_CONFIG7]: 0x00000f00
    GPMC CS 3 Registers
    [GPMC_CONFIG1]: 0x00001000
    [GPMC_CONFIG2]: 0x00101001
    [GPMC_CONFIG3]: 0x00020201
    [GPMC_CONFIG4]: 0x10031003
    [GPMC_CONFIG5]: 0x010f1111
    [GPMC_CONFIG6]: 0x8f030000
    [GPMC_CONFIG7]: 0x00000f00
    GPMC CS 4 Registers
    [GPMC_CONFIG1]: 0x00001000
    [GPMC_CONFIG2]: 0x001e1e01
    [GPMC_CONFIG3]: 0x00080300
    [GPMC_CONFIG4]: 0x1c091c09
    [GPMC_CONFIG5]: 0x04181f1f
    [GPMC_CONFIG6]: 0x00000fcf
    [GPMC_CONFIG7]: 0x00000f6d
    GPMC CS 5 Registers
    [GPMC_CONFIG1]: 0x00001000
    [GPMC_CONFIG2]: 0x001e1e01
    [GPMC_CONFIG3]: 0x00080300
    [GPMC_CONFIG4]: 0x1c091c09
    [GPMC_CONFIG5]: 0x04181f1f
    [GPMC_CONFIG6]: 0x00000fcf
    [GPMC_CONFIG7]: 0x00000f6c
    GPMC CS 6 Registers
    [GPMC_CONFIG1]: 0x00001000
    [GPMC_CONFIG2]: 0x00101001
    [GPMC_CONFIG3]: 0x00020201
    [GPMC_CONFIG4]: 0x10031003
    [GPMC_CONFIG5]: 0x010f1111
    [GPMC_CONFIG6]: 0x8f030000
    [GPMC_CONFIG7]: 0x00000f00
    GPMC CS 7 Registers
    [GPMC_CONFIG1]: 0x00001000
    [GPMC_CONFIG2]: 0x00101001
    [GPMC_CONFIG3]: 0x00020201
    [GPMC_CONFIG4]: 0x10031003
    [GPMC_CONFIG5]: 0x010f1111
    [GPMC_CONFIG6]: 0x8f030000
    [GPMC_CONFIG7]: 0x00000f00

  • Hi David,

    About the usage of the readmem tool:

    root@android:/ # readmem

    Usage:  readmem [-8|-16|-32] <reg_addr> [value]

    Enter only the register address for dumping its value: readmem <reg_addr>
    Enter the register address and value for setting a new value: readmem <reg_addr>  <value>

    BR

    Tsvetolin Shulev

  • So is this tool meant to be used on a host linux machine? Or the target while it runs a linux kernel?

    I've made some progress with being able to read from the ethernet chip. It appears we needed to do some additional configurations with regards to a power management chip that connects to our ethernet chip.

    However, our ethernet driver is having problems with the irq. According to our board documentation, our ethernet chip IRQ is connected to GPIO163. From my understanding, that would mean we need to enable bit 3 from GPIO6 GPIO_IRQENABLE1 register, is that correct? Are there other registers we should set to get this IRQ setup correctly?

  • The readmem tool must be used on the target board while it runs a linux kernel.

    You can read the description of usage of the IRQ setup in the TRM section - 25.5.3 Interrupt and Wakeup at the link below but you correctly understood the mechanism of work of it.

    http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf

    BR

    Tsvetolin Shulev