I am porting a mature application from the C6416 to a C6455. The application uses PCI, EDMA, EMIF, McBSP and cache. The port is mostly complete but a difficult problem with McBSP0 remains. Generally speaking the McBSP XMT operation is reliable. However, there is a rare, intermittent failure where writing to the McBSP XDR register appears either very slow or blocked altogether. There is some evidence that this condition is correlated with significant activity on the PCI bus. The situation has been observed when XDR is written by the CPU as well as EDMA3.
The following code runs reliably for significant period but eventually results in a condition where a McBSP transmission is not sent. It would appear that the XDR write fails but the read of the status signal is not blocked although it may be incorrect.
#define MCBSP0_CONFIG_BUS_DXR0 (*(volatile unsigned int*) (0x028C0004u))
for (i=0;i<count; i++) {
while (!(pMcbsp0_Regs->SPCR & XRDY)) {}
MCBSP0_CONFIG_BUS_DXR0=*uintDataPtr;
uintDataPtr ++;
}
The following code also runs reliable but ultimately does fail. It does not result in a lost xmt message but it does cause the program to miss a real-time deadline. It appears that the message gets sent but successful writing of the message to the XDR register incurs significant latency.
for (i=0;i<count; i++) {
while (!(pMcbsp0_Regs->SPCR & XRDY)) {}
MCBSP0_CONFIG_BUS_DXR0=*uintDataPtr;
// Wait here until write acknowledged
while (MCBSP0_CONFIG_BUS_DXR0 != * uintDataPtr) {}
uintDataPtr ++;
}
I have tried accessing the XDR register with both the configuration bus and EDMA bus with identical results. If anyone can shed light on this situation I would appreciate it greatly.
Thanks,
Paul