Generating interrupts through Hyperlink

Hi,

1) yes, it is possible. we already confirmed interrupt packet transaction between DSPs. CIC0 has output ports to various cores. you can map the input from VUSR to the output for core 0 ~ 3

2) yes, the CIC0 input is fixed to 111

3) HW supports 64 different input source and we also have SW generated interrupt option for us to issue any interrupt. the detail is described in UG.

Regards,

Albert

Hi,

Thanks for your quick reply.

Just to make sure we are talking about the same thing; in the same program, I want to configure the Hyperlink interrupts so that local core 0 can trigger an interrutp on remote core 0 and, a few moments later, local core 0 can trigger an interrupt on remote core 1.

I don't want local core 0 to trigger an interrupt on both remote core 0 and remote core 1 at the same time.

I'm telling you this because, in my mind, since the CIC0 input is fixed to 111 there is no way to distinguish which core, on remote device, the interrupt was destined to.

How do you do that ?

David

I already answered this. please see our data manual Interrupt chapter. it shows each GEM core have 18 inputs from CIC0 but the output port number of CIC0 is different for each Core. it depends on your CIC0 input output mapping configuration which GEM core you want to use for Hyperlink interrupt. please read INTC UG to get more information about CIC programming.

Regards,

Albert

1) Hyperlink user guide, p. 39/85 it is said :

The vector field is either indicates
which bit of the remote pending register to set or used as an index to get
interrupt address depending on the int2cfg setting at the remote device.

I set my int2cfg to zero. So the vector will be used as an index to get interrupt address according to the guide.
There is no further explanation about how this is used.I've read the CIC and interrupt controller guides but I haven't found anything relevant.
Can you clarify this point ?

2) I've been studying your 3326 Hyperlink Interrupt example and especially these lines :

#ifdef iLoopModeOn
     *((int *)CSL_MCM_CR) |= 0x00006080;//intlocal = 1, intenable = 1(module status int), intvec = 0, int2cfg =1
#else
     *((int *)CSL_MCM_CR) |= 0x00002080;//intlocal = 0, intenable = 1(module status int), intvec = 0, int2cfg =1
#endif

     //Interrupt control index register
     *((int *)CSL_MCM_INTCI) |= 0x00000001;//icidx = 1
     //Interrupt control value register
     *((int *)CSL_MCM_INTCV) |= 0x88000001;//inten = 1, sien = 1, vector = 1 (for SW interrupt)
     //Interrupt pointer index register
     *((int *)CSL_MCM_INTPI) |= 0x00000001;//icidx = 1
     //Interrupt pointer value register
     *((int *)CSL_MCM_INTPV) |= 0x0000014;//intptr = 0x14 for int pending register

     // Generate soft interrupt value register
     *((int *)CSL_MCM_GSFTINT) |= 0x00000001;//ivector = 1

Hyperlink documentation p. 41/85, paragraph 2.7.5.3 Interrupt Mapping; It is said :

When int2cfg is clear, the interrupt status is extracted from the
received interrupt packet and written to the register indicated by the Interrupt Pointer
Register for the particular micro processor select (MPS) value.

2)a. I don't understand why you write 0x0000014 in this register. Please clarify this point.

2)b. What is actually moved/written to the register pointed by Interrup Pointer Register is the vector field ?

Regards,

David

David,

1) "I set my int2cfg to zero. So the vector will be used as an index to get interrupt address according to the guide" I found some problems long time ago while checking this feature and I think it is related with SoC level connection issue. please only use  int2cfg == 1 option for your test.

2a) I set int2cfg to 1, so LSB 8 bits shows the address offset of Interrupt Pending/Set Regsiter of Hyperlink and it is 0x14 currently. (see register map)

2b) No it is not vector. In the example, I set vector to one and it is matched with interrupt pointer register pair index number. again 0x14 is the address offset of Hyperlink register.

regards,

albert