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The relation of internal TSCL/TSCH and external Timer

Allen Lee
Genius 3770 points

Hi All,

I am working on a DM6467EVM board, and I want to test the execution time of a piece of my code. There may be two ways, the TSCL/TSCH register inside C64x+ and the external Timer module. 

TSCL/TSCH works on the DSP clock and timer works on SYSCLK3 which is 1/4 of DSP clock. What I want to know is that could we think they are synchronous and one timer cycle is exactly equals to 4 TSCL/TSCH cycles?  If there is some situation like memory access blocking, I think timer could also take the latency into account, but could TSCL/TSCH also do that? 

Thanks.

Allen