C6748 EMIFA nand flash poor performance

Jan,

Is the 150MHz EMA_CLK confirmed at that output pin?

What are the settings for the EMIF timing registers?

What are the timing requirements for your NAND device?

Regards,
RandyP

Hello RandyP,

I am not able to measure on pin B7 EMA_CLK, unfortunately this pin is not connected on PCB.

Today I am not able to debug with device and read directly EMIF timing register, but I tested LCDK nand example with following parameters

#define NAND_WRITE_SETUP_TIME_IN_NS (0u)
#define NAND_WRITE_STROBE_TIME_IN_NS (30u)
#define NAND_WRITE_HOLD_TIME_IN_NS (30u)
#define NAND_READ_SETUP_TIME_IN_NS (20u)
#define NAND_READ_STROBE_TIME_IN_NS (40u)
#define NAND_READ_HOLD_TIME_IN_NS (0u)
#define NAND_TURN_ARND_TIME_IN_NS (0u)

  I tried also modify those parameters, but it has not much influence when the read period is 600ns and I chnage 20-30ns.

I will check and post exact EMIF timing registers values from debug in few days.

Regarding NAND device requirements it is able to handle read/write signal period down to 20ns according to datasheet.

Best Regards 

Jan

Hello,

below is screenshot of EMIFA registers values, it looks like CE3CFG register uses reset values instead of values defined by macros.

Is any possibility to check EMIFA clock without measurement on EMIFA_CLK pin, like from some registers values?

Can anybody suggest how to propperly setup EMIFA and speed up nand flash memorry communication?

I am using nand_c674x_c6748_lcdkC6748 example project from starterware for testing.

Thanks.

Jan

Jan,

You do not need to check the EMA_CLK. With the values shown in CEnCFG, all of your timing parameters are set to their reset and maximum values, so that is why you timing is so slow.

The problem is not with the hardware but with the software not writing the values you want into those registers.

Please start from a working example, look through your software, and you can try to find what has changed from that example to your own software.

Regards,
RandyP