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SerDes Clock Mult for SGMII on C6674

Martin Leister
Prodigy 100 points
Other Parts Discussed in Thread: TMS320C6674

We would like to interface the SGMII port of a TMS320C6674 to the Marvel 88E1112 Ethernet Transceiver. It appears that the SGMII SERDES on the 6674 requires an external SGMII clock of 312.5, 250 or 156.25 MHz. The 88E1112 provides a 625 MHz SGMII Receive Clock (S_CLK) for use by PHY.

Can the C6674 interface to the 88E1112 without externally dividing down the 625 MHz from the 88E1112?

 

  • 0
    TI__Mastermind 46460 points

    Martin,

    No, the top frequency allowed into the SGMII SERDES is 312.5MHz.

    Tom

     

  • 0
    TI__Mastermind 42545 points

    The 625MHz receive clock is provided by the 88E1112 specifically as an input into MAC devices with SGMII interfaces that do not recover the clock from the receive data stream. This clock was part of the SGMII specification but most MAC devices with SGMII interfaces, including the C6674, will recover the clock and don't need the 625MHz receive clock. The receive clock is not intended to be used as a SGMII reference clock and won't work with the C6674. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Prodigy 100 points

    Bill -

    Thanks for the response.

    Just to confirm I understand, we need to provide a 156.25, 250 or 312.5 MHz to the C6674 SRIOSGMIICLK input, and that will be used by the SGMII SerDes PLL to recover the clock from the serial data from the 88E1112 PHY? And the supplied clock does not have to be from, or derived from, the 88E1112, since the PLL takes care of any phase differences between the supplied clock and the input serial data?

    Regards,

    - Marty

  • 0 in reply to Martin Leister
    TI__Mastermind 42545 points

    The SRIOSGMIICLK input is the source for the PLLs inside the SGMII and SRIO IP blocks. The output of the PLL is used for clock recovery from the receive data, as a source clock for the transmit data and as the clock for the rest of the logic within that block. It does not have to be derived from any clock used by the 88E1112. Be sure that it meets the phase noise requirements needed. 

    Regards, Bill