AM335x cache coherence procedures

Hi,

From a document for the TMS320C674x describing the cache and how it works (Cache User's Guide) I got the information that buffers need to be aligned and n times the size of a cache line.
Now StarterWare includes functions like "CacheDataInvalidateBuff()" and "CacheDataCleanBuff()" to get the memory and cache coherent. Both functions allow to tell how many bytes to be invalidated/cleaned.
Question: Should this number of bytes be n times the size of the cache line or does the functions correct the value to n times the size of the cache line?

Example: Is this correct (?):

CacheDataInvalidateBuff(&buffer[0], 3);

or should it be:

CacheDataInvalidateBuff(&buffer[0], 64);

Thanks.

Best regards,
Patrick