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Problem with McBSP in master mode

Pavel Yazev
Prodigy 20 points

Other Parts Discussed in Thread: DM3730

I’m trying to setup MASTER mode McBSP for I2S interface.

I use DM3730 microprocessor and McBSP3 port. Software platform is Linux.

The McBSP control registers have next values:

 

SPCR2: 0x02f5

SPCR1: 0x0031

RCR2:  0x0041

RCR1:  0x0040

XCR2:  0x0041

XCR1:  0x0040

SRGR2: 0x101f

SRGR1: 0x0f3d

PCR0:  0x0f0f

 

All necessary bits for master mode are set.

If I run the port for transmitting or receiving I see clock and frame pulses on appropriate microprocessor pins.

In the case of transmitting all works correctly.

But in the case of receiving port doesn’t receive any data.

I check this by RRDY bit in SPCR1 register. RRDY bit is always 0.

But if I switch port into digital loopback mode (DLB = 1) it starts to receive own data.

It seems clock or frame pulses aren’t routed correctly when DLB=0. 

DM3730 has five serial ports. They are initialized similar way by the same Linux driver.

I’ve tried to do similar experiment with the rest of the ports.

McBSP1 and McBSP2 work as expected.

But receiving doesn’t work on McBSP2, McBSP4, McBSP5.

I’ve tried set EXTCLKGATE bit in XCCR but this hasn’t changed situation.

 

I'm in a standoff.

Any advise please.

 

Thanks.

Pavel.

 

  • 0
    TI__Guru 65405 points

    Hi Pavel,

    I check the configuration of the McBSP control registers and it seems correct. Perhaps the problem is due to other part of the code. I'm not excluding some hardware issue but it is the last possible reason. You can try to make some debug log for further investigation.

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 20 points

    Hi Tsvetolin,

     

    Thank you for the reply.

    The McBSP control registers must be correct because McBSP1 and McBSP2 work properly with this settings.

    I use Linux 2.6.37 kernel which is originally from PSP 04.02.00.07

    It’s difficult for me to realize what kind of debug information would be helpful.

    I made a few McBSP’s driver modifications to reduce the problem just to reading RRDY status.

    One more fact. For McBSP3 I see that bit RFSR (Receive Frame Synchronization) in IRQSTATUS_REG is set.

     

    I hope there is somebody who has managed to get McBSP  master mode working or has failed as me.

    Such evidences would be useful.

     

    BR,

    Pavel