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PCIe en x1 mode

Delared Delared
Expert 1945 points

Hi,

I’m trying to perform pcie transactions between 2 shannons and evaluate the throughput performance in both x1/x2 mode and Gen1/Gen2 [Based on TI LLD] and I have a problem in x1 mode!

  1. Code:

  /* Setting PL_GEN2 */  

  memset (&setRegs, 0, sizeof(setRegs));

  gen2.numFts = 0xF;

  gen2.dirSpd = 0x0; // Gen1=0x0 ||| Gen2=0x1

  gen2.lnEn   = 1; // x1 mode =1 ||| x2 mode =2

  setRegs.gen2 = &gen2;

                                    

  if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)

  {

    System_printf ("SET GEN2 register failed!\n");

    return retVal;

  }

  1. using CPU, I can’t look the difference, say that  is normal because the throughput performance of CPU is limited by Data payload size (4B) and the efficiency is about 11%. right ???
  2. But Using EDMA:

- throughput (Gen2) is about 2x throughput (Gen1) OK

- throughput x2  is always equal to throughput x1 (about 5.53 Gbps in Gen2 & 2.7 Gbps in Gen1) => NOK!!

 So, how can I change PCIe link to x1 mode ? (gen2.lnEn   = 2 don’t work !!)

PS: I’m using the BOC, and may I ask if the BOC can have an effect on PCIe link mode (x1 or x2) ?

 

  • 0
    TI__Guru* 95265 points

    Delared,

    You can refer to an application note: http://www.ti.com/lit/an/sprabk8/sprabk8.pdf sections 5 and 6 for example codes how to set-up x1 or x2 lane. The PCIE throughput was tested by using BOC to connect two C66x cards, for gen1/gen2, x1/x2. The BOC shouldn't cause any problem.

    Regards, Eric 

  • 0 in reply to lding
    Expert 1945 points

    Eric,

    in the doc sprabk8, section 5 i found:

    switch (lane_num) {
    Case 1: //single lane
    PL_LINK_CTRL[LINK_MODE] = 0x1; //enable x1 lane
    Case 2: //two lanes
    PL_LINK_CTRL[LINK_MODE] = 0x3; //enable x2 lanes
    }

    the TI LLD defines:

    uint16_t pcieGen2Reg_s::lnEn

    [rw] Lane enable. 1h=x1, 2h=x2. Other values reserved.

    Field size: 9 bits


    so we talk about  the same thing non ???

    however, the problem persists and i got no difference between x1 & x2 !!

  • 0 in reply to Delared Delared
    TI__Guru* 95265 points

    Delared,

    Please configure the following 3:

    1)MAX_LINK_WIDTH bitfield of LINK_CAP register (0x2180107c) set to 1.

    2)LNK_MODE bitfield of PL_LINK_CTRL register (0x21801710) set to 1. ==========>This is the example in sprabk8

    3)LN_EN bitfield of PL_GEN2 register (0x2180180c) set to 1. ========> This is the PCIE LLD

    After link is up, you can check the LINK_STAT_CTRL register (0x21801080) to see what you actually got. NEGOTIATED_LINK_WD field will show the link width (lane number, 0x1=x1 lane, 0x2=x2 lane) and LINK_SPEED field will show the link rate (0x1=GEN1, 2.5Gbps; 0x2=GEN2, 5.0Gbps).

    Regards, Eric