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DM8168 DDR flying adder 4 & 5

Andrew Dyer
Intellectual 650 points

Is it safe to disable flying adders 4 and 5 in the DDR clock area on DM8168 via the DDRPLL_PWD register?

The two are shown as spare in figure 7-4 in the datasheet, however they are configured and operational in the u-boot source code (DDRPLL_FREQ4, DDRPLL_DIV4, DDRPLL_FREQ5 and DDRPLL_DIV5 registers).

If they do need to be configured, what do they affect and what is the range of clock settings that will work?

  • 0
    TI__Guru**** 170625 points

    Hi Andrew,

    I think it is safe to disable DDR PLL clock 4 and 5. From within u-boot I write the value of 0x00000030 in register DDRPLL_PWD (at address 0x48140444), then I boot the linux kernel and mount root fs successfully, I do not observe any issues.

    Also, this thread states the same: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/138259/499318.aspx

    "these are spare clocks that shouldn't be needed"

    Regards,

    Pavel