Hi,
I have prototype board incorporating the C6678 DSP and am testing the SPI boot capability of the device.
I have an N25Q28A11ESF Nor Flash device on the board and have tried to implement spi boot through the methods outlined in the following thread:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/115298.aspx?pi74271=4
I have built my own .dat and .bin files as discussed in the above thread but I have also tried to use the provided .dat file in the attached zip files. I have an EVM board and have no issues in running the Nor writer over the on board emulator and seeing the resulting changes in reg A1 on the device after boot in SPI mode. Once I try to reproduce the test on my own board, I can not see the same desired result and it seems nothing has changed. I am using the external emulator XDS560v2.
I have quickly probed the EVM board and my prototype and it seems that both boards are writing to the flash with no obvious differences. There is an issue though when I try to boot from SPI on my prototype board as I see the DSP is sending data to the FLASH continuously and the clock is also running continuously.
I am using the follwing boot table:
section {
boot_mode = 50
param_index = 0
options = 1
core_freq_mhz = 800
exe_file = "simple.i2c.ccs"
next_dev_addr_ext = 0x0
sw_pll_prediv = 5
sw_pll_mult = 32
sw_pll_postdiv = 2
sw_pll_flags = 1
addr_width = 24
n_pins = 4
csel = 0
mode = 0
c2t_delay = 0
bus_freq_mhz = 0
bus_freq_khz = 500
}
The c6678 device is rev 2 silicon.
Would there be an issue where the ibl for the EVM is configuring more than just the PLL fix on the board? I am confused as to the settings required for the pll, should the values be based on CLK = CLKIN × (PLLM+1) ÷ (OUTPUT_DIVIDE × (PLLD+1))?
Is there anything you can suggest to help me pin point what my issue may be?
Regards,
Fearghal
