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thanks Biser for the information! I post it again at below,
We have tried to change register "SDRC_DLLA_CTRL" to expand CDL phase ( fixed delay). Unfortunately, nothing changed with different register value:
1) Original value (same with TI EVM board) - 0xC
2) Changed to 0x4000000C, 0xC000000C (just delay phase is changed)
3) Changed to 0x8 (tracking mode)
Hi Echo,
Have you check out the following links before:
http://processors.wiki.ti.com/index.php/AM3715/03_SDRC_Subsystem
http://processors.wiki.ti.com/index.php?title=Setting_up_AM37x_SDRC_registers
Thanks!
yaoming