Is the GPMC_ERR_ADDRESS register reset by the GPMC_ERR_TYPE.ERRORVALID bit?
The GPMC_ERR_ADDRESS register is able to Write.
What meaning does it have to write?
Does it clear those bits to write?
Best regards,
Daisuke
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Is the GPMC_ERR_ADDRESS register reset by the GPMC_ERR_TYPE.ERRORVALID bit?
The GPMC_ERR_ADDRESS register is able to Write.
What meaning does it have to write?
Does it clear those bits to write?
Best regards,
Daisuke
Are the GPMC_ERR_ADDRESS.ILLEGALADD bits reset by the GPMC_ERR_TYPE.ERRORVALID bit?
The GPMC_ERR_ADDRESS.ILLEGALADD bits can be written.
After these bits were written, what occurs?
AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. H)
http://www.ti.com/lit/ug/spruh73h/spruh73h.pdf
7.1.5.7 GPMC_ERR_ADDRESS (Page 371)
Best regards,
Daisuke
Hi,
Is it a typo in the TRM that the GPMC_ERR_ADDRESS.ILLEGALADD bits are R/W (Read/Write)?
Is it correct that the GPMC_ERR_ADDRESS.ILLEGALADD bits are R (Read only)?
AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. H)
http://www.ti.com/lit/ug/spruh73h/spruh73h.pdf
7.1.5.7 GPMC_ERR_ADDRESS (Page 371)
Best regards,
Daisuke
Hi,
Once I wrote "0x7FFFFFFF" to the GPMC_ERR_ADDRESS.ILLEGALADD field, the GPMC_ERR_ADDRESS register was changed from "0x00000000" to "0x400000AC" and the GPMC_ERR_TYPE register was changed from "0x00000000" to "0x00000211".
Therefore I guess the GPMC_ERR_ADDRESS.ILLEGALADD bits are R (Read only).
Is my guess correct?
Best regards,
Daisuke