Hi,
I recently developed my own design incorporating many of the features of the TI TMSC6678 design. During testing of one of my working prototypes I have recently run into errors where I cannot now test the device using CCS.
This board initially worked fully using both the external emulator and on board emulator without any issue. I was trying to test the SPI Boot on my board and decided to just test the norwriter_evm6678 project. I initially tested it by running the project as it was and there were no issues so then I checked for example projects that could give me outputted results to confirm it operates fine.
I had quickly reviewed the HUA demonstration and tried to run the application since I believed that this was related to the Nor writer and would potentially lead me to be able to develop my own application to test the NOR flash boot. I ran the software from the section “Write Nor Flash”. I did not configure the IBL since I thought it was not necessary if I wanted to boot directly from Flash: (http://processors.wiki.ti.com/index.php/MCSDK_Image_Processing_Demonstration_Guide#Multicore_booting_using_MAD_utilities)
I had the USB onboard emulator and an Ethernet connection to the DSP. The setup is basically the same as the 6678 EVM board. I had PuTTY terminal emulator open as well but once I ran the norwriter and then tried to boot in spi mode, I received an error. Since then I have received errors on the board as I have outlined below. I realize I should not have taken this path since the section is titled booting the application from IBL.
Would you be able to tell me how to fix my DSP or what the issue may be? I have outlined the setups I have tested and the console outputs I am seeing:
1) Development board placed on a Virtex 7 FPGA carrier for power only– direct connection over USB to on board emulator. Loading of the target configuration with no issue. Console output:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: XXXX
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x0000000F
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
2) Run the test connection utility on this setup and also see no errors:
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\Users\Fearghal\AppData\Local\.TI\693494126\
0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Oct 3 2012'.
The library build time was '21:58:41'.
The library package version is '5.0.872.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
There is no hardware for programming the JTAG TCLK frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
There is no hardware for measuring the JTAG TCLK frequency.
-----[Perform the standard path-length test on the JTAG IR and DR]-----------
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
-----[Perform the Integrity scan-test on the JTAG IR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
-----[Perform the Integrity scan-test on the JTAG DR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End]
3) However when I try to run the Global_Default_Setup script I get the following error:
C66xx_0: GEL Output: C6678L GEL file Ver is 2.004
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ...
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: Trouble Writing Memory Block at 0x210000dc on Page 0 of Length 0x4: (Error -150 @ 0x210000DC) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 5.0.872.0)
Global_Default_Setup() cannot be evaluated.
target access failed
at *((unsigned int *) (0x21000000+0x000000DC))=0x80000000 [evmc6678l.gel:261]
at ddr3_setup_auto_lvl_1333(0) [evmc6678l.gel:841]
at Global_Default_Setup_Silent() [evmc6678l.gel:1540]
at Global_Default_Setup()
IcePick_D: Error: (Error -150 @ 0x0) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 5.0.872.0)
IcePick_D: Unable to determine target status after 20 attempts
IcePick_D: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
C66xx_0: JTAG Communication Error: (Error -150 @ 0x0) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 5.0.872.0)
C66xx_0: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
4) CSS then freezes and I need to stop it in windows task manager. Once I start up the software again I load the same on board target emulator configuration from step 1 with no issue. I then try and load the nowriter_evmc6678l project. Once I try this I get the following console output:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: XXXX
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x0000000F
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL: File: C:\Users\Fearghal\workspace_v5_3\norwriter_evmc6678l\bin\norwriter_evm6678l.out Does not match the target endianness, not loaded. Check project build options and target configuration file (ccxml).
5) So I power cycle the board and try to load the norwriter_evmc6678l project again. This time there are no issues:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: XXXX
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x0000000F
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.
However when I run the program I get the following error:
[C66xx_0] NOR Writer Utility Version 01.00.00.03
NOR device open failed!
Returned platform error number is 17
This indicates that the flash routines did not recognize the flash manufacturer. This was not an error I saw before the board started to fail on me.
6) I finally ran the platform_utils_test that is used for the evm after power cycling the board once more and saw no errors. The following was seen on the console output:
[C66xx_0] p_info->version = 1.00.00.00
p_info->cpu.core_count = 8
p_info->cpu.name = TMS320C6678
p_info->cpu.id = 21
p_info->cpu.revision_id = 0
p_info->cpu.silicon_revision_major = 0
p_info->cpu.silicon_revision_minor = 0
p_info->cpu.megamodule_revision_major = 8
p_info->cpu.megamodule_revision_minor = 1
p_info->cpu.endian = 1
p_info->board_name = 667
p_info->frequency = 1000
p_info->board_rev = 65535
p_info->led[PLATFORM_USER_LED_CLASS].count = 0
p_info->led[PLATFORM_SYSTEM_LED_CLASS].count = 0
p_info->emac.port_count = 2
EMAC port 1 connected to the PHY.
MAC Address = 00:17:ea:ca:0c:e9
NOR Device:
p_device->device_id = 47896
p_device->manufacturer_id = 32
p_device->width = 8
p_device->block_count = 256
p_device->page_count = 256
p_device->page_size = 256
p_device->spare_size = 0
p_device->handle = 47896
p_device->flags = 0
p_device->bboffset = 0
EEPROM Device (@ 0x50):
p_device->device_id = 80
p_device->manufacturer_id = 1
p_device->width = 8
p_device->block_count = 1
p_device->page_count = 1
p_device->page_size = 65536
p_device->spare_size = 0
p_device->handle = 80
p_device->flags = 0
p_device->bboffset = 0
Current core id is 0
User switch 1 state is OFF
EEPROM test start
test_eeprom: Write test data failed, errno = 0x4
EEPROM test complete
NOR test start
test_nor: passed
NOR test complete
Internal memory test start
Internal memory test (for core 2) passed
Internal memory test complete
External memory test start
Memory Size is 1GBytes
External memory test passed
External memory test complete
Test completed
7) When I tried to run the test again I got the following error on the console:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: XXXX
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x0000000F
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.
C66xx_0: Error: (Error -150 @ 0x0) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 5.0.872.0)
IcePick_D: Error: (Error -150 @ 0x0) One of the FTDI driver functions used during configuration returned a invalid status or an error. (Emulation package 5.0.872.0)
IcePick_D: Unable to determine target status after 20 attempts
IcePick_D: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
There was no change after a power cycle of the board. I received the same error twice more. I do not understand why it would work the first time.
I also tested the board with the external emulator. I tried to repeat the tests that were carried out for the onboard emulator :
1) Development board placed on a Virtex 7 FPGA carrier for power only – direct connection over the external emulator (spectrum digital XDS560v2 STM). I cannot load my external target configuration. Console output:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
IcePick_D: GEL: File: C:\Users\Fearghal\workspace_v5_3\platform_test_667\Debug\platform_test_667.out Does not match the target type, not loaded.
2) But when I run the test connection utility on this setup I see no errors:
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\Users\Fearghal\AppData\Local\.TI\693494126\
0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 560/2xx-class product.
This utility will load the program 'sd560v2u.out'.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Oct 3 2012'.
The library build time was '22:14:17'.
The library package version is '5.0.872.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 none - 01 00 500.0kHz - similar isit internal clock
2 none - 01 09 570.3kHz - similar isit internal clock
3 512 - 01 00 500.0kHz O good value measure path length
4 128 - 01 00 500.0kHz O good value auto step initial
5 128 - 01 0D 601.6kHz O good value auto step delta
6 128 - 01 1C 718.8kHz O good value auto step delta
7 128 - 01 2E 859.4kHz O good value auto step delta
8 128 + 00 02 1.031MHz O good value auto step delta
9 128 + 00 0F 1.234MHz O good value auto step delta
10 128 + 00 1F 1.484MHz O good value auto step delta
11 128 + 00 32 1.781MHz O good value auto step delta
12 128 + 01 04 2.125MHz O good value auto step delta
13 128 + 01 11 2.531MHz O good value auto step delta
14 128 + 01 21 3.031MHz O good value auto step delta
15 128 + 01 34 3.625MHz O good value auto step delta
16 128 + 02 05 4.313MHz O good value auto step delta
17 128 + 02 13 5.188MHz O good value auto step delta
18 128 + 02 23 6.188MHz O good value auto step delta
19 128 + 02 37 7.438MHz O good value auto step delta
20 128 + 03 07 8.875MHz O good value auto step delta
21 128 + 03 15 10.63MHz O good value auto step delta
22 128 + 03 1E 11.75MHz {O} good value auto step delta
23 512 + 02 3E 7.875MHz O good value auto power initial
24 512 + 03 0E 9.750MHz O good value auto power delta
25 512 + 03 16 10.75MHz O good value auto power delta
26 512 + 03 1A 11.25MHz O good value auto power delta
27 512 + 03 1C 11.50MHz O good value auto power delta
28 512 + 03 1D 11.63MHz O good value auto power delta
29 512 + 03 1D 11.63MHz O good value auto power delta
30 512 + 03 13 10.38MHz {O} good value auto margin initial
The first internal/external clock test resuts are:
The expect frequency was 500000Hz.
The actual frequency was 499110Hz.
The delta frequency was 890Hz.
The second internal/external clock test resuts are:
The expect frequency was 570312Hz.
The actual frequency was 569214Hz.
The delta frequency was 1098Hz.
In the scan-path tests:
The test length was 16384 bits.
The JTAG IR length was 6 bits.
The JTAG DR length was 1 bits.
The IR/DR scan-path tests used 30 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 11.75MHz as the highest frequency.
The IR/DR scan-path tests used 10.38MHz as the final frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
The frequency of the JTAG TCLKR input is measured as 10.37MHz.
The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
The target system likely uses the TCLKO output from the emulator PLL.
-----[Perform the standard path-length test on the JTAG IR and DR]-----------
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
-----[Perform the Integrity scan-test on the JTAG IR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
-----[Perform the Integrity scan-test on the JTAG DR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End]
3) I then try and load the nowriter_evmc6678l project using the external emulator configuration. Once I try this I get the following console output:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: XXXX
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x0000000F
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.
When I run the program however I get the following error again:
[C66xx_0] NOR Writer Utility Version 01.00.00.03
NOR device open failed!
Returned platform error number is 17
4) I then try and load the nowriter_evmc6678l project again using the external emulator configuration. I try to run the Global_Default_Setup script and I get the following error::
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: XXXX
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x0000000F
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.
C66xx_0: GEL Output: C6678L GEL file Ver is 2.004
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ...
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ...
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: Trouble Writing Memory Block at 0x2620038 on Page 0 of Length 0x4: (Error -180 @ 0x0) The controller has detected a target power loss. The user must turn-on or connect the power supply for the target. (Emulation package 5.0.872.0)
Global_Default_Setup() cannot be evaluated.
target access failed
at *((unsigned int *) (0x02620000+0x0038))=0x83E70B13 [evmc6678l.gel:168]
at configSGMIISerdes() [evmc6678l.gel:857]
at Global_Default_Setup_Silent() [evmc6678l.gel:1540]
at Global_Default_Setup()
C66xx_0: Power Failure on Target CPU
C66xx_0: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
5) I finally ran the platform_utils_test that is used for the evm again and saw the following console ouput:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: XXXX
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x0000000F
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL: File: C:\Users\Fearghal\workspace_v5_3\platform_test_667\Debug\platform_test_667.out Does not match the target endianness, not loaded. Check project build options and target configuration file (ccxml).
6) So I power cycled the board once more and ran the test again and now have the following:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: XXXX
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x0000000F
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.
IcePick_D: Power Failure on Target CPU
C66xx_0: Power Failure on Target CPU
C66xx_1: Power Failure on Target CPU
C66xx_1: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
7) I power cycled the board once more, disconnected the external emulator and reset it. I connected everything again and ran the program and had no errors:
[C66xx_0] p_info->version = 1.00.00.00
p_info->cpu.core_count = 8
p_info->cpu.name = TMS320C6678
p_info->cpu.id = 21
p_info->cpu.revision_id = 0
p_info->cpu.silicon_revision_major = 0
p_info->cpu.silicon_revision_minor = 0
p_info->cpu.megamodule_revision_major = 8
p_info->cpu.megamodule_revision_minor = 1
p_info->cpu.endian = 1
p_info->board_name = 667
p_info->frequency = 1000
p_info->board_rev = 65535
p_info->led[PLATFORM_USER_LED_CLASS].count = 0
p_info->led[PLATFORM_SYSTEM_LED_CLASS].count = 0
p_info->emac.port_count = 2
EMAC port 1 connected to the PHY.
MAC Address = 00:17:ea:ca:0c:e9
NOR Device:
p_device->device_id = 47896
p_device->manufacturer_id = 32
p_device->width = 8
p_device->block_count = 256
p_device->page_count = 256
p_device->page_size = 256
p_device->spare_size = 0
p_device->handle = 47896
p_device->flags = 0
p_device->bboffset = 0
EEPROM Device (@ 0x50):
p_device->device_id = 80
p_device->manufacturer_id = 1
p_device->width = 8
p_device->block_count = 1
p_device->page_count = 1
p_device->page_size = 65536
p_device->spare_size = 0
p_device->handle = 80
p_device->flags = 0
p_device->bboffset = 0
Current core id is 0
User switch 1 state is OFF
EEPROM test start
test_eeprom: Write test data failed, errno = 0x4
EEPROM test complete
NOR test start
test_nor: passed
NOR test complete
Internal memory test start
Internal memory test (for core 2) passed
Internal memory test complete
External memory test start
Memory Size is 1GBytes
External memory test passed
External memory test complete
Test completed
If I try and run again, I get the same failure as above:
C66xx_0: Power Failure on Target CPU
C66xx_1: Power Failure on Target CPU
C66xx_1: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
