We're using the DM8148 as a PCIe endpoint. The RC is a standard Intel core I3 based PC running with AMI BIOS & windows 8. Our issue is that the DM8148 endpoint is not always enumerated by the host and is therefore invisible to the OS. For our product to be viable, we need the DM8148 to reliably enumerate as a PCIe endpoint on our PC based RC host. We're aware of the recently posted errata regarding PCIe boot mode via RBL, and our plan has always been to configure the DM8148 PCIe endpoint via MLO loaded via SD card.
We've tested the DM8148 via the Mistral EVM and our custom board. The Mistral EVM has had the external PCIe ref clock modification. We've also tried a different host (pentium 4 based PC). We use PSP 4.04.00.01 and the EZSDK (the RDK does not support PCIe, and we've worked with DM8148 since the first EZSDK release). This PCIe enumeration testing is performed by powering on DM8148 board, then powering on the PC host in that order. Our DDR3 runs @ 400Mhz, and the ARM core @600Mhz. Both our EVM & our custom board use parts marked 'X8148X3874BCYE' which is revision 2.1 silicon. We've instrumented MLO with a few status dumps.
Following power on of the DM8148, we see MLO pause after enabling the PCIe PLL. When the Intel PC host powers on, we see MLO's PLL lock message and MLO completes PCIe endpoint initialization.
We have tried the following DM8148 endpoint configurations and received the results shown:
32 bit with 4k/8M/16M/8k/8k bars ==> enumerates successfully 40% of power on attempts
64 bit with 4k/256M/1GB bars ==> enumerates successfully 50% of power on attempts
The EVM and our custom boards both show similar results. Curiously, we can obtain ~80% success with an EVM in 64b mode 4k/256M/1GB bars running RBL only, though the host PC bios restarts numerous times on 50% of the attempts (and also attempts PCIe re-allocation via asserting the discrete PCIe reset signal which toggles POR on the EVM. Our custom board also allows discrete PCIe reset to toggle POR).
To eliminate the possibility that there is an Intel host RC BIOS issue, we allowed the system to boot to windows. With the DM8148 unplugged, we powered the DM8148 board on, observed the board waiting for PLL lock, and then hot plugged the DM8148 into the Intel host PCIe bus. Again, we tried both the EVM and our custom board. The success percentage went up slightly for a success rate of 50-60% depending on configuration. This is still far short of the 100% we need.
For comparison, performing cold boot or hot plug of a standard Intel GB ethernet card results in a 100% success rate for enumeration with the same host RC in the same slot.
We've used the windows based "PCIscope" SW package to monitor and report DM8148 PCIe resource information on the RC. On the DM8148, MLO can provide confirmation that PCIe endpoint configuration completed. We are in the process of obtaining a PCIe bus analyzer to gather more information. We can't determine right now if the RC is issuing "hot-reset" or "disable-link" transactions over PCIe to the DM8148.
We realize that the DM8148 PCIe endpoint requires SW initialization, and hope that this issue can be addressed via changes to the PCIe initialization. The higher success rate on the EVM running RBL only might imply that MLO is taking too long to prepare the DM8148 endpoint, but this is only a theory.
Please advise on suggestions to debug this issue further. If there is any information we can supply to provide you with better insight, let us know.
Thanks for the help,
Jim D.
