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PCIe Read Access Problem

g.f.
Guru 15520 points


Hi,

I'm having a problem with C6678 PCIe.

C6678 and FPGA are connected with PCIe.
C6678 is Root Complex and FPGA is End Point.

I'm just trying to Write/Read to/from FPGA by C66x CPU.

After writing data(0xFEFFFFFF) to Addr:0x60000000,
reading data from Addr:0x60000000 the result is 0xFE7FFFFF.
The upper bit9 data is not appropriate.

At this state, I check the Addr:0v60000000 from CCS Memory Browser.
The result was 0xFE7FFFFF which is not appropriate.
But when I refreshed the Memory Browser, the data was changed to 0xFEFFFFFF which I wrote.

What kind of thing will cause this problem?
Should I insert "a few cycle delay" between write access and read access?

best regards,
g.f.

  • 0
    TI__Genius 12065 points

    May I ask is it always bit 23 gives error or some other random data pattern please?

    When you directly write data into the PCIe data space (starting from 0x6000_0000) in CCS Memory Browser, are you able to read back the data correctly without refresh please?

    In your application, the PCIe data space is not setup as cacheable region, is it? 

    If possible, could you share your code of the sequence for the DSP/FPGA memory write and read please?

  • 0 in reply to Steven Ji
    Guru 15520 points

    Hi Steven,

    Thank you for the response.
    And I'm sorry, the problem has been solved.

    The problem was not C6678, it was FPGA.

    best regards,
    g.f.

  • 0 in reply to g.f.
    Intellectual 505 points

    Hi g.f,

    I am trying to implement PCIe interface between TMS320TCI6670 and ALTERA Cyclone 4 FPGA. Through one of the posts, I understood that you have implemented the pcie and fpga interface. I have gone through the PCIeexampleproject, But I have some issues in understanding the code. I have understood that the root complex maps the data from the source buffer to the Pcie base address and outbound address translation from pcie base address 0x60000000 to 0x70000000, as outbound address is 0x70000000. How you initialized your FPGA Endpoint. In my case the FPGA BAR 1 and 2 has 0x00200000 to 0x00200FFF. If i put this address as my DSP outbound address(replacing 0x70000000 to 0x00200000), is it enough?. Can you please share how you done the interface testing. Your kind help is appreciated.

    Thank You,

    Regards,

    Nithin B