Hi, all,
I use EDMA3_LLD to transfer data, currently, DDR 2 DDR transfer is OK, but DDR to L2 is failed - the destination on L2 not changed after EDMA completed.
In my case, the DDR is cached, so, the following two lines use to make them coherency.
Edma3_CacheFlush((uint32_t)chCfg->srcAddr, len);
Edma3_CacheInvalidate((uint32_t)chCfg->dstAddr, len);
It is the same code for DDR 2 DDR and DDR 2 L2, just change the destination address from DDR to L2. and the L2 address is the global address, such as 0x10800000.
BTW, L2 is config as SRAM only, and #pragma DATA_ALIGN(dst, EDMA3_CACHE_LINE_SIZE_IN_BYTES) also used for the dst.
Any suggestion for the issue?
Thanks a lot.
BRs,
Matt
