AM3517 CPU-L3-DDR read latency

Rainier Lamers

Other Parts Discussed in Thread: AM3517

Does anybody know where to find out more about the L3 latencies on an AM3517 chip ?

My issue is that on a cache miss it takes around 330nS to return a DDR RAM read (about 250nS with Data cache disabled so no line fill).

I'm clocking MPU at 600Mhz, L3 at 166Mhz. DDR at 166Mhz (verified clock frequency). Current u-boot initialization code. What am I missing ? Why is this so slow ?

Rainier

over 12 years ago

0 Jeff L over 12 years ago

TI__Expert 5960 points

Hi Rainier,

We measure DDR latency on our AM3517 on our EVM's internally.

For AM3517, we have measured 283 ns.

We use LMBench in our Linux SDK to measure this value. The name of the test is lat_mem_rd. The test copies a small block of data repeatedly and measures latency.

Then the test increases the block size and repeats the test until the block size reaches 1MB. You can see three distinct latencies L1, L2 and DDR.

This link has an example for a different part: http://processors.wiki.ti.com/index.php/LMBench_on_ARM_Microprocessors

Processors

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AM3517 CPU-L3-DDR read latency