PLL adjustment causing failure

Hi,

What is a power failure? Is CPU down? 

Can you try to modify GEL file to 1MHz  to check there is some bug in your C code?

Regards,

Hyun

Hi Hyun,

  I modified the GEL file to 1MHz and the emulator connected just fine.  I validated that the correct pll register values were set for 1MHz clock rate.  I then stepped into my code and attempted to set the pll back to bypass reconfigure the pll mult and pll post div to 1MHz and it fails again on the pll enable. 

Thanks,

Will

Hi Hyun,

  I set the breakpoint at the pll enable line.  I then step over the hw register call and I get the power failure.

Will

Hi Will,

What I meant was to set a break point after pll enable. Can you try it? Also what is power failure?

Hyun

Hi Hyun,

  I set the breakpoint after

HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) |= PLLC_PLLCTL_PLLEN;

I never reached the breakpoint and the error I receive in the console window states

C674X_0: Power Failure on Target CPU

C674X_0: Failed to remove the debug state from the target before disconnecting.  There may still be breakpoint op-codes embedded in program memory.  It is recommended that you reset the emulator before you connect and reload your program before you continue debugging

Thanks,

Will

Hi,

Can you check your code that is equivalent to Gel file?

/* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
PLL0_PLLCTL &= ~(0x00000020); ==> HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLENSRC;

/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
PLL0_PLLCTL &= ~(0x00000200); ==> HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_EXTCLKSRC;

/* Set PLLEN=0 to put in bypass mode*/
PLL0_PLLCTL &= ~(0x00000001);    ==> HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLEN;

Hyun

Yes my #defines match what you posted.  Attached is the pllSupport.h file.

Will

2742.pllSupport.zip

Hi,

Please try attached file. It's from gel file.

Regards,

Hyun