Hello everyone,
I'm working on the EVM C6678 with Sys/bios. We use L1P and L1D as cache, all L2 as SRAM.
First, let me know if I'm wrong on the following points :
a) by default the MAR (128 to 159) bits are set to 0, meaning the DDR3 is not cacheable.
b) they need to be set to 1 to become cacheable.
c) you can set cacheability statically with GEL files or CFG ; dynamically with Sysbios cache module or with the CSL.
On the GEL files supplied with the MCSDK I can read :
(*( unsigned int* )( MAR128 )) = 0xD;
I was expecting 0x1 (to turn cacheability on) or 0x0 (to turn it off) but I don't get why 0xD.
What does 0xD mean ? is DDR3 cacheability on with this setting ?
Thank you,
CM
