TMS320C6657 timers programming

You can start with the CSL examples for Timer and Interrupt controller.

Please take a look at the example folder of C6678 CSL (C6657 CSL folder seems not have those examples), such as:

C:\ti\pdk_C6678_1_1_2_5\packages\ti\csl\example\timer

The CSL API usage should be the same between C6678 and C6657. In your project, you could use the C6657 CSL library.

Please note the timer numbers in the example as well since C6657 may not have as many timer as C6678.

The timer CSL example also includes one watchdog timer example. You can get a general idea of how to enable the CPU interrupt and Timer event based on that as well.

could you please give me a link to download it?
thank you!

Hi Steven,

  I am trying to get a watchdog timer to work on the 6657 evm.  The input clock is 100MHz but I don't know which system clock drives the timers.  Timer 0 is used by sysbios so I guess I would use timer 1 for the watchdog.  I am using the 6678 watchdog example.  I don't plan to use an interrupt, instead I plan to have a high priority task which just sleeps for 1 second, and then pets the watchdog timer if no errors have occurred.  Could you please let me know which system clock timer 1 uses.  Also, is the period register updated every system clock or every 1ms?

Thanks,

Will

Giannis,

You can download the BIOS MCSDK in the following link which includes the C66x PDK/CSL packages:

http://www.ti.com/tool/bioslinuxmcsdk

Will,

All the chip level Timers in C66x devices are running at SYSCLK7 frequency (CPU clock / 6), i.e. if the CorePac clock (SYSCLK1) is running at 1GHz after PLL, the SYSCLK7=1GHz/6.

Please note that Timer 0 is dedicated to Core0 and Timer 1 is dedicated to Core1 as watchdog timer mentioned in section 7.19 Timers in C6657 data manual.

The timer counter will increase by 1 every 6 CPU cycles, since the timer clock is (CPU clock)/6.

Hi Steven,

  Thanks for the response.  So there should not be a problem using Timer 0 for watchdog even though BIOS is also using TIMER 0?

Thanks

Will

Will,

The Timer user guide states "Once the timer is configured as a watchdog timer, it cannot be reconfigured as a GP timer until a device reset occurs." (Chapter 4).

So when you use Timer0 as a watchdog timer, it could be a problem for BIOS to use the same timer as a general-purpose timer. 

Maybe you could choose another global Timer for BIOS usage since there are 8 chip level Timers in C6657.

That was my next question which was how many timers does the 6657 have.  I know that the 6678 had 8 so I didn't know if the 6657 had the same or less.  I saw the statement about the watchdog not being able to be a GP timer so that is why I was a bit concerned. 

Thanks,

Will

Hi Steven,

  I am just now implementing the watchdog timer on the 6657 core 0.  It says that only timer 0 can be configured for a watchdog timer for core 0.  Timer 0 is already configured by the bios so how can I create a watchdog timer for core 0?  In the datasheet it says that timers 2-7 are only general purpose.

Thanks,

Will

Hi Steven,

 So I was able to move the BIOS clock to timer 3.  I configured Timer 0 to be the watchdog.  I believe I followed the steps for activating the watchdog because I used the exact same steps on our c6748 which I know works.  The watchdog never restarts the eval board.  Any thoughts?  The count values are always at 0.  My TGCR register is set to 0x1B.  Does the eval board support a watchdog timer reset?

Will

The OMODE was the problem.  I couldn't find any documentation describing the reset muxing.

Will