Hello
i am tring to run DSP codec engine examples on DSP on DM8168. I found some problems when i run at the same time capture_encode and universal_copy. I read the following forums:
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/149505.aspx
I use the default memory map from http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map. I modified the files:
1) remote.cfg in apps/universal_copy
//Processor.heapId = common.MessageQ_heapMap["Ipc"];
//Processor.sharedRegionId = common.SharedRegion_map["Ipc"];
Processor.heapId = 0; // <-- Don't know why
Processor.sharedRegionId = common.SharedRegion_map["SysLink: HOST<--->DSP"];
2) serverplatforms.xs in servers/all_codecs
var TI816X_DSP_ExtMemMap = {
/*
DDR3_HOST: {
comment: "DDR3 Memory reserved for use by the A8",
name: "DDR3_HOST",
base: 0x80000000,
len: 0x0B000000 // 176 MB
},
DDR3_DSP: {
comment: "DDR3 Memory reserved for use by the C674",
name: "DDR3_DSP",
base: 0x8B000000,
len: 0x01800000 // 24 MB
},
DDRALGHEAP: {
comment: "DDR3 Memory reserved for use by algorithms on the C674",
name: "DDRALGHEAP",
base: 0x8C800000,
len: 0x00800000 // 8 MB
},
DDR3_SR1: {
comment: "DDR3 Memory reserved for use by SharedRegion 1",
name: "DDR3_SR1",
base: 0x8D000000,
len: 0x00C00000 // 12 MB
},
DDR3_HDVPSS: {
comment: "DDR3 Memory reserved for use by HDVPSS",
name: "DDR3_HDVPSS",
base: 0x8DC00000,
len: 0x00200000 // 2 MB
},
DDR3_V4L2: {
comment: "DDR3 Memory reserved for use by V4L2",
name: "DDR3_V4L2",
base: 0x8DE00000,
len: 0x00200000 // 2 MB
},
DDR3_SR0: {
comment: "DDR3 Memory reserved for use by SharedRegion 0",
name: "DDR3_SR0",
base: 0x8E000000,
len: 0x01000000 // 16 MB
},
DDR3_M3: {
comment: "DDR3 Memory reserved for use by the M3 core",
name: "DDR3_M3",
base: 0x8F000000,
len: 0x01000000 // 16 MB
},*/
DDR3_DSP: {
comment: "DDR3 Memory reserved for use by the C674",
name: "DDR3_DSP",
base: 0x99500000,
len: 0xc00000 /* 12 MB (Default memory reserved for c674x changed based on size of the DSP code)*/
},
DDRALGHEAP: {
comment: "DDR3 Memory reserved for use by algorithms on the C674",
name: "DDRALGHEAP",
base: 0x98000000,
len: 0x00400000 /* 4 MB (Region used by algs and codec engine for memory allocations) */
},
DDR3_SR1: {
comment: "DDR3 Memory reserved for use by SharedRegion 1 (IPC)",
name: "DDR3_SR1",
base: 0x99400000,
len: 0x00100000 /* 1 MB */
},
DDR3_SR0: {
comment: "DDR3 Memory reserved for use by SharedRegion 0 (SYSLINK)",
name: "DDR3_SR0",
base: 0x9F700000,
len: 0x00200000 /* 2 MB */
},
};
3) remote.cfg in buidutils
/* first set module defaults ... */
//Processor.heapId = common.MessageQ_heapMap["Ipc"];
//Processor.sharedRegionId = common.SharedRegion_map["Ipc"];
Processor.heapId = 0; // <-- Don't know why
Processor.sharedRegionId = common.SharedRegion_map["SysLink: HOST<--->DSP"];
/* ... then add per-processor settings */
var coreComm = {};
coreComm.numMsgs = 64;
coreComm.msgSize = 4 * 1024;
coreComm.heapId = Processor.heapId;
coreComm.userCreatedHeap = false;
coreComm.sharedRegionId = Processor.sharedRegionId;
if (platform.match("TI814X") || platform.match("TI816X") ||
platform.match("DM8148") || platform.match("DM8168")) {
Processor.coreComm.$add(coreComm);
Processor.coreComm.$add(coreComm);
//Processor.coreComm.$add(coreComm);
//Processor.coreComm.$add(coreComm);
}
4) ti_platforms_evmTI816x.cfg in servers/all_codecs
/*
var entry2 = new SharedRegion.Entry();
entry2.base = ipcSharedMem.base;
entry2.len = ipcSharedMem.len;
entry2.ownerProcId = MultiProc.getIdMeta("HOST");
entry2.isValid = true;
entry2.createHeap = true;
entry2.cacheEnable = true;
entry2.name = "IpcShared";
SharedRegion.setEntryMeta(
common.SharedRegion_map["Ipc"],
entry2
);*/
5) The load script configuration is this:
echo "Loading PRCM & SYSLINK"
prcm_config_app s
modprobe syslink
until [[ -e /dev/syslinkipc_ProcMgr && -e /dev/syslinkipc_ClientNotifyMgr ]]
do
sleep 0.5
done
echo "Loading CMEM for C674 Firmware"
modprobe cmemk phys_start=0x96C00000 phys_end=0x97ffffff pools=20x4096,10x131072,2x1048576
echo "Loading HDVICP2 Firmware"
firmware_loader $HDVICP2_ID /usr/share/ti/ti-media-controller-utils/dm816xbm_m3video_whole_program_debug.xem3 start -mmap /usr/share/ti/ti-media-controller-utils/mm_dm81xxbm_vc3.bin -i2c 0
echo "Loading HDVPSS Firmware"
firmware_loader $HDVPSS_ID /usr/share/ti/ti-media-controller-utils/dm816xbm_m3vpss_whole_program_debug.xem3 start -mmap /usr/share/ti/ti-media-controller-utils/mm_dm81xxbm_vc3.bin -i2c 0
Questions:
- If i set heapId=3 in remote.cfg (like the forum) the application does not start. If i set this value to 0 the application runs. Why? The application runs while capture_encode is running.
- Why in the forum i have to comment the 2 Processor.coreComm.$add(coreComm); ? What does this function do?
Problems:
When i run the universal application and the capture_encode is running there are no errors. When the capture_encode stop i can see this trace and the systems crashes.
tearing down the capture-encode example
exiting thread
exiting thread
exiting thread
exiting thread
got eventState changed to: OMX_StateIdle
capture state idle
got eventState changed to: OMX_StateIdle
DEI state idle
got eventState changed to: OMX_StateIdle
display state idle
got eventState changed to: OMX_StateIdle
display control state idle
got eventState changed to: OMX_StateIdle
Encoder state idle
got eventState changed to: OMX_StateLoaded
display state loaded
got eventState changed to: OMX_StateLoaded
ctrl-dc state loaded
got eventState changed to: OMX_StateLoaded
encoder state loaded
got eventState
Unable to handle kernel paging request at virtual address d6000008
changed to: OMX_pgd = c6cac000
StateLoaded
d[d6000008] *pgd=00000000ei state loaded
Deallocate buInternal error: Oops: 5 [#1]
last sysfs file: /sys/devices/platform/omap/omap_i2c.2/i2c-2/2-0010/resolution
Modules linked in: dma_mmap mt9m031 ti81xxvin ti81xxvo ti81xxfb vpss cmemk syslink ipv6
CPU: 0 Not tainted (2.6.37+ #4)
PC is at HeapMemMP_free+0x1c8/0x400 [syslink]
LR is at GateMP_enter+0x80/0xa0 [syslink]
pc : [<bf099634>] lr : [<bf094eb4>] psr: 60000013
sp : c6435e60 ip : 00000000 fp : c6435e94
r10: 00151800 r9 : 00000000 r8 : bebf29d4
r7 : d6000008 r6 : d37e6000 r5 : d6000080 r4 : d6000000
r3 : 00000000 r2 : 00000000 r1 : 00060000 r0 : 00000000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c5387d Table: 86cac019 DAC: 00000015
Process capture_encode_ (pid: 1333, stack limit = 0xc64342e8)
Stack: (0xc6435e60 to 0xc6436000)
5e60: d6000080 00151800 c6435e94 00000000 c01cf35a bebf29d4 0000000f bebf29d4
5e80: c6434000 00000000 c6435ef4 c6435e98 bf0cfe38 bf099478 c01cf35a bebf29d4
5ea0: 00000000 d37e3000 80000080 00151800 40138450 bebf2a1c 0010ee20 0000ac2c
5ec0: c6435eec a0000013 c6435ef4 c6435ed8 c01e5020 c0069cac c64459f0 00000000
5ee0: c6c4a880 0000000f c6435f04 c6435ef8 c00d3c34 bf0cfcac c6435f74 c6435f08
5f00: c00d4344 c00d3c18 40277000 c6421e00 c01e1ab0 c6677c40 50db1fee 33428f00
5f20: c00545c0 c6421e00 40277000 c6435f70 0000003c 40277000 c6434000 00000000
5f40: 00000001 0000003c 00000000 00000000 bebf29d4 c01cf35a 0000000f c6c4a880
5f60: c6434000 00000000 c6435fa4 c6435f78 c00d43dc c00d3e50 00000000 00000001
5f80: 50db1fee bebf29d4 c01cf35a 000f9518 00000036 c0046fa8 00000000 c6435fa8
5fa0: c0046e00 c00d4390 bebf29d4 c01cf35a 0000000f c01cf35a bebf29d4 00000001
5fc0: bebf29d4 c01cf35a 000f9518 00000036 00000000 00000000 4009b000 bebf2abc
5fe0: 000f952c bebf29a8 00086efc 40208aec 20000010 0000000f 00000000 00000000
Backtrace:
[<bf09946c>] (HeapMemMP_free+0x0/0x400 [syslink]) from [<bf0cfe38>] (HeapMemMPDrv_ioctl+0x198/0x77c [syslink])
[<bf0cfca0>] (HeapMemMPDrv_ioctl+0x0/0x77c [syslink]) from [<c00d3c34>] (vfs_ioctl+0x28/0x44)
r6:0000000f r5:c6c4a880 r4:00000000
[<c00d3c0c>] (vfs_ioctl+0x0/0x44) from [<c00d4344>] (do_vfs_ioctl+0x500/0x540)
[<c00d3e44>] (do_vfs_ioctl+0x0/0x540) from [<c00d43dc>] (sys_ioctl+0x58/0x7c)
[<c00d4384>] (sys_ioctl+0x0/0x7c) from [<c0046e00>] (ret_fast_syscall+0x0/0x30)
r8:c0046fa8 r7:00000036 r6:000f9518 r5:c01cf35a r4:bebf29d4
Code: e3a01008 e30f2fff e3a03001 ebff66a7 (e5940008)
ffers capture 0,---[ end trace 42c3b980df6544ae ]---
ptr 0x44818080, size 1382400
Thanks for the help