• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 98 subscribers
  • Views 423 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6678 SRIO alignment

Peter Robertson
Expert 2770 points

The SRIO document SPRUGW1B is unclear about alignment requirements for transfers as it is never clear where it is talking about the internals of the device and its user interface.

Does the value written into LSU Reg2 (the DSP address) have to be a multiple of 8?

Is the answer the same for all packet types?

  • 0
    TI__Mastermind 23525 points

    Peter,

    No the DSP address field is a byte aligned address field.  This applies to all packet types handled by the LSU.  I described how the LSU will actually break up and create the needed packets to send across the SRIO link on this thread...

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/251493/880424.aspx#880424

    The SWRITE checks are simple, it must be a multiple of a double word payload size (8B) and it must be programmed for a double word aligned address in LSU_Reg1 (add[2:0]=000).  NWRITEs have more alignment options because of the wdptr/wdsize packet fields.  Basically, the rules below make sure the data is contiguous in memory and can be sent in SRIO packets (compliant to the address being 8B aligned with wdptr/wdsize).  Our LSU implementation on segmenting packets calls it invalid if you try to do a <8B transfer that would take more than one SRIO packet to the same 8B aligned address.  The RapidIO standard made this a little more complicated than it had to be, but it is what it is.

    Regards,

    Travis

    Addr[2:0]

    Len

    000

    >=1

    001

    1

    >=7

    010

    1

    2

    >=6

    011

    1

    >=5

    100

    1

    2

    >=4

    101

    1

    >=3

    110

    1

    >=2

    111

    >=1
  • 0 in reply to tscheck
    Expert 2770 points

    Thanks for that, but I'm afraid your post raises more questions as it sems to answer both no and yes.  Also your diagram is open to misinterpretation: to which address does 'addr' refer (R1, R2, or both), which command (NREAD, SREAD...) , and is the right-hand column a list of acceptable options or something else?

    To try to avoid even more questions I shall give some explicit examples that cover my cases of interest.

    Which of the following are valid C6678 LSU register combinations?

    A: r1=0, r1=0x10800004, r2 = 0x11800004, r3 = 8, r5=NREAD
    B: r1=0, r1=0x10800004, r2 = 0x11800004, r3 = 8, r5=NWRITE
    C: r1=0, r1=0x10800004, r2 = 0x11800004, r3 = 4, r5=NREAD
    D: r1=0, r1=0x10800004, r2 = 0x11800004, r3 = 4, r5=NWRITE

    If there are restrictions on the values that can be put in the registers, it would have been sensible to list them explicitly in one place in the documentation (preferably where it talks about how those registers are used).

    Regards,

    Peter

  • 0 in reply to Peter Robertson
    TI__Mastermind 23525 points

    Peter,

    As I mentioned above, the DSP address in LSU_Reg2 can have any value.  You can read or write to local memory based on a byte aligned address.

    LSU_Reg1 address has the restrictions that I list in the table above based on the byte count written to LSU_Reg3.  ADDR[2:0] refers to address in LSU_Reg1.  As an example, if you wanted to write 3B with an NWRITE, RapidIO defines only two combinations of address + wdptr/wdsize that will work.  The address that is sent in the packet is ALWAYS 8B aligned, so the valid byte lanes for 3B would be the first three bytes or the last three bytes of the the 8B aligned address.  If this is confusing look at the RapidIO standard spec Part 1, table 4-4 in the Rev 2.1 specification.  Translating this to the table I gave you, for sending 3B, you must specify LSU_reg1 address to end in either:

    ADDR[2:0] = 000 (results in 1 packet being sent) or

    ADDR[2:0] = 101 (results in 1 packet being sent) or

    ADDR[2:0] = 110 (results in 2 packet being sent) or

    ADDR[2:0] = 111 (results in 2 packet being sent)

    These are valid, sending two packets for quantities <8B is ok as long as the 8B aligned address can change from one packet to the next.  I will clarify that in my above statement and mark in red.

    SWRITE is defined in the RapidIO spec as always a multiple of 8B, so ADDR[2:0]=000.  There is no SREAD.  NWRITE/NREAD can access sub 8B quantities.

    Peter Robertson said:
    A: r1=0, r1=0x10800004, r2 = 0x11800004, r3 = 8, r5=NREAD
    B: r1=0, r1=0x10800004, r2 = 0x11800004, r3 = 8, r5=NWRITE
    C: r1=0, r1=0x10800004, r2 = 0x11800004, r3 = 4, r5=NREAD
    D: r1=0, r1=0x10800004, r2 = 0x11800004, r3 = 4, r5=NWRITE

    I'm assuming your first r1 is actually LSU_Reg0 and second r1 is LSU_Reg1...

    A) Valid - takes 2 packet requests/responses

    B) Valid - takes 2 packet requests

    C) Valid - takes 1 packet request/response

    D) Valid - takes 1 packet requests

    Regards,

    Travis

  • 0 in reply to tscheck
    Expert 2770 points

    Thanks, that makes it clear.

    Regards,

    Peter