I've tried a specific UART configuration and test in Linux of AM335X.
1. I use UART interrupt mode.
2. I set UART FIFO disabled. up->fcr &= ~UART_FCR_ENABLE_FIFO;
3. The SDK code of UART driver in Linux: up->scr = OMAP_UART_SCR_TX_EMPTY, which means the THR interrupt shall be generated when TX FIFO empty and TX shift register empty(refer AM335x user manual 19.5.1.27).
4. I also modify the code of "transmit_chars" in "omap-serial.c" to make sure in THR interrupt handler function, if THR interrupt occurs, only one byte be written to THR register.
5. When I use an application to write 4 bytes to this UART port, only 2 bytes be sent. I also use oscilloscope to catch the TX signal, it shows only 2 bytes be sent.
My question is:
1) If the register SCR[TXEMPTYCTLIT] is set to 1, shall the THR interrupt be generated when TX FIFO empty and TX shift register empty?
If it is, it doesn't make sense in my case. I think it could be a mistake about the description of user manual, it could be THR interrupt be generated when TX FIFO empty or(not and) TX shift register empty.
2) If shift register is not empty, but TX FIFO is empty, at that time, does it make any data lose or data error to write a byte to THR register?
3) If FIFO disables, TX FIFO is not empty, how about the behaior to write a byte to THR at that time? The byte written to THR shall be lost?
