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DM816x NOR flash support - TRM queries

Sharath Kumar Bhat38979
Intellectual 300 points

We have a query on NOR flash supported by GPMC of DM816x processor. Under the section 25.7.2 XIP Memory of the TRM (Literature Number: SPRUGX8B March 2013), it says that “Can connect up to 1 Gbit (128 Mbytes) memories”. Also we see that each GPMC chip select can support up to 256 MB of memory.

 Based on the above observation we have few queries,

  1. Is this 128 MB limitation mentioned under section 25.7.2  is due to RBL limitation?
  2. If this limitation is due to RBL, then is this limitation of 128 MB applicable even if we interface a SPI EEPROM/Flash for booting
  • 0
    TI__Genius 9101 points

    It is a typo – RBL does not impose any limitation, other than the pinmux setting that are done by the ROM code – during boot up, ony 4KByte of the NOR is available. The pinux code of the UBL must reside in this 4KByte, and this can open up the pin mux for the remaining pins.

     The GPMC supports A0-A27 pins, which translated into 256Mbytes of NOR memory for each chip slect.

     As SPI EEPROM is not directly addressable, this restriction does not apply to SPI memories. However, the RBL SPI ROM supports booting only using 24bit addressing, so this would limit the size to 16Mbyte, if boot from SPI is needed.

    regards
    Kedar

  • 0 in reply to Kedar Chitnis
    Intellectual 650 points

    Dont forget to set the remaining address lines to an appropriate value on your board with pullup/pulldown resistors or else live with the fact that your boot code will be located at the address dictated by the default pullup/pulldown state of the higher order address lines you choose to hook up.