EDMA LLD and C6670

Aymeric,

aymeric dupont said:

There is an example provided by Texas Instruments to do so configuring manually the DMA from the host.

aymeric dupont said:

This was a good starting point but I want now creating a mechanism to monitor the "link" in a more efficient way. In brief this "link" is using a set of tasks, message queues and memory buffers to pass the data from SRC to DEST... Withing this link, data can be transferred from SRC (on host) to C6670  and from C6670 to DEST(on the C6670)

Have you considered the QMSS and Packet DMA to do these transfers? It might fit well with what you are trying to do. But that is a new thread for someone else to help you with.

aymeric dupont said:

1) can I use the EDMA LLD driver if one of the address is not in the C6670 memory (L1/L2/DDR). I mean can the SRC or DST be at 0x6000 0000 which are the 256MB of PCIe data.

Please check the datasheet for the Memory Map and the Connection Matrix to determine which bus masters can access which peripherals. I am confident that you can do this transfer that you want to do.

aymeric dupont said:

2) I have my transfer mechanism set up and working where I am doing memcpy. This does: transfer from SRC to mem1 and transfer from mem1 to DEST. All buffers are 1024 bytes. All buffers are in DDR.

The first transfer is ok:    TransferData(channel,1,(SSP_UINT32)wr_buf,(SSP_UINT32)rd_int_buf, BUFF_SIZE);
The second transfer fails    TransferData(channel,2,(SSP_UINT32)rd_int_buf,(SSP_UINT32)rd_buf,BUFF_SIZE);

You may need to explain a lot more about what you are doing here. 'memcpy' sounds like a DSP-based copy instead of an EDMA3-based copy.

Cache does not directly affect the operation of the EDMA3, but cache can affect how a DSP or CorePac accesses the data that is the source or destination of a DMA transfer.

Take a look through your code to see how the EDMA3_ENABLE_DCACHE value is being used. It appears to me that this #define is only used in the calling functions that you write, or that are in the examples. It does not appear to be used inside the library functions. So if changing this value changes the way your code operates, it must be enabling cache coherency operations in your code.

aymeric dupont said:

3) If my address is at 0x6000 0000, should I use these functions? Edma3_CacheFlush and Edma3_CacheInvalidate on these addresses?

It is not common to have cache enabled for peripheral memory addresses. So in the common case, you would not need to use those commands for that address range.

But if you do enable cache for that address range by setting the relevant MAR bits (see the CorePac User Guide for more information), then you will need to use these functions.

aymeric dupont said:

4) What interrupt vectors and events and levels are used for the EDMA interrupts? Where is this section being configured? Is it using CSL or SysBios?

The EDMA3_LLD is supposed to help you with this. Does the example you are using implement an interrupt? If it does, then you can use the documentation (comments) and code to see how to do this.

Regards,
RandyP

Hey Randy,

First of all, thanks for getting back to me. It seems that you have a huge knowledge in this area and I hope you can point me to the right direction. So first let me answer your questions, then I will continue with my questions.

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1) the example provided by TI is in the MCSDK: mcsdk_2_01_00_03\tools\boot_loader\examples\pcie\linux_host_loader\. Not in the EDMA LLD examples. From this example, I understood that the EDMA can be configured to carry data from a host to a target over PCIe.

2) From the data manual, in the functional block, it seems that the PCIe and the EDMA are connected by the TeraNet. Furthermore, the Switch Fabric Connections Matrix indicates that they are connected via a bridge.

3) I therefore do not see problem transferring data using the EDMA engine. Considering that the EDMA has something like 256 channels, I do not see any need to use QMSS (which I am very unfamiliar with) to do so. However the mechanism I described is similar to QMSS but in software.

4) I can explain you a lot more about the code I am writing if you want me to but I do not think it is relevant (for now) to my questions. If you wish, I can send you a high level description block of my design but not on the forum.

Let me answer your question. You are again correct, memcopy is a DSP based copy. This is the simplest "copy" that I can use to validate my design. I do not want to use memcopy because I wish to reduce the CPU load. I want to use DMA transfers that I set in a few cycles and work alone.

The best solution is the EDMA driver which I am currently studying and using as is. I wish not to have to rebuild this package..

However, I am very confuse about three specific items.

a) Where is the BIOS or CSL being used (since I want to understand what happen when I register my handlers and do not want my code to conflict with the EDMA see http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices)

b) The cache that seems to be needed at the application level and that I did not even knew it existed before I saw the following in the cache manuals:

At boot time L2 cache is disabled and all of L2 is configured as SRAM (addressable internal memory). If DSP/BIOS is used, L2 cache is enabled automatically; otherwise, L2 cache can be enabled in the program code by issuing the appropriate chip support library (CSL) command: CACHE_L2SetSize();

c) What is the DAT example doing and if I need it.

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I hope I provided the information you were looking for and that you can provide me better pointers or explanation to the three point above. Now I wish to continue asking about the cache.

As far as I (and twiki) know, A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. In my case, all my memory is in external memory and they are cyclic buffers which change all the time. Therefore I am not sure I need to cache anything. But BIOS use cache by default.

As far as you told me, the use of cache is only at the application level. But this is how the example on the C6670 is provided. I did not change anything in my application.

So my question is do I need to use cached memory to use the EDMA driver properly? If I do not use these 2 APIs Edma3_CacheFlush(src) and Edma3_CacheInvalidate(dest), do you know why the transfer is failing.

Thanks so much for you help. I really appreciate the time you will invest to provide me a bit more knowledge about these subjects.

Aymeric

Aymeric,

My apologies for the long delay. We may be able to find someone more suitable than I am to help you, since I am not reaching a very good understanding of your situation.

If the EDMA3_ENABLE_DCACHE switch makes your code work, then it is certainly needed. This switch tells the application code to use cache coherency commands before or after the DMA transfer. I believe this is not done in the library, but in the source code that you use in your application.

It will be best to have caching disabled for the PCIe memory mapped region that starts at 0x6000 0000. Make sure the MAR register bits for that region are cleared

The DAT example uses QDMA to do a transfer. That is probably not what you want to do.

The amount of cache used is set in your platform file. I assume you are using SYS/BIOS and not DSP/BIOS, right? And you want to use as much cache as your application will allow, so check the settings in your platform file and max out the L2 cache if you do not require L2 for SRAM.

I think many of your questions will be best answered by turning to the training material we have online, and to the documentation such as the EDMA3 LLD Drivers User Guide, C6678 Data Manual, CorePac User Guide, Cache User Guide, and EDMA3 User Guide. That is a lot of material, and you will probably be able to find the parts that apply to your questions and look at those parts more closely.

I hope this helps.

Regards,
RandyP