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SRIO RIO_DEVICEID_REG

In SPRUGW1B table 2-5 it mentions RIO_DEVICEID_REG0..15 and has the footnote: "** Note that RIO_DeviceID_Regn are an input to the logic layer, and are not its memory map." (I assume there should be an 'in' in there).

In section 2.3.12 RX Multicast and Multiple DestID Support it state: "The device’s main baseID (0x1060) is now automatically copied into the RIO_DEVICEID_REG1 by
hardware, and does not require a separate write by software.".

These two comments are consistent, but say nothing about how registers 2..15 are set.

Later in the same document (2.3.15.3 Peripheral Initializations) it has:

// Set Device ID Registers
rdata = SRIO_REGS->DEVICEID_REG1;
wdata = 0x00ABBEEF;
mask = 0x00FFFFFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->DEVICEID_REG1 = mdata ; // id-16b=BEEF, id-08b=AB
rdata = SRIO_REGS->DEVICEID_REG2;
wdata = 0x00ABBEEF;
mask = 0x00FFFFFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->DEVICEID_REG2 = mdata ; // id-16b=BEEF, id-08b=AB

This contradicts the statements above. Where is DEVICEID_REG1? Is it in the memory map (as implied by the code above) or is it not (as stated in table 2-5)?

A note on page 2-2 states: "DeviceID Register 1 through DeviceID Register 15 inherit their values from the Base Routing Registers".

As there appear to be only 4 such Base Routing Registers, how can sixteen DEVICEID registers be set by them?

  • Peter,

    Clearly some cleanup is needed here.  Thanks for posting.  Let me straighten some things out...

    First the Note on page 2-2 is correct.. "DeviceID Register 1 through DeviceID Register 15 inherit their values from the Base Routing Registers" (RIO_PLM_SPn_BRR_n_PATTERN_MATCH & RIO_PLM_SPn_BRR_n_CTL)

    Note that 0x1B3A0 and 0x1B3A4 are not supported, i.e. you can't read/write them.  Instead..

    RIO_DEVICEID_REG0 inherits its value from RIO_BASE_ID, which is 0xB060 not 0x1060 as it was in C64x devices.

    Only the Base Routing Registers and RIO_BASE_ID are read/writable (memory mapped), RIO_DEVICEID_REG0-15 are not directly read/writable, they hold the values of the other registers that I mention.

    Note that the BRR registers are per port, i.e. there are 4 PATTERN_MATCH and 4 CTL registers per port.  Within the CTL register, there is a PRIVATE bit which determines if the corresponding PATTERN_MATCH register is used for just that port or all ports.  Just set it to 0b0 for all ports.  This will give you the 15 deviceIDs, plus the BASE_ID value.

    Regards,

    Travis