• State
  • Locked Locked
  • Replies 0 replies
  • Subscribers 97 subscribers
  • Views 255 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Cacheability setting for L2 global address

H Lee
Prodigy 90 points

Hello,

I want to enable cache for L2 memory with C6678 and CCS 5.0.1.

According to the corepac user guide document, PC of MAR0 is always 1, so L2 is cacheable.

But, if I want to use global address for L2 (ex, 0x10800000, 0x11800000, etc), what should I do?

I set the memory segment of each core to global address in RTSC platform. (We don't use local address, so it is not defined as memory segment)

The document explains that the default PC value of MAR16 is 0, but if I run without any MAR bit setting, the PC value of MAR16 is 1.

Is MAR16 used for L2 global address or other purposes and why is the PC of MAR16 is set to 1?

 

Thanks.