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C6657 needs nPOR assertion before Full Reset?

Nori Shinozaki
Intellectual 2430 points
Other Parts Discussed in Thread: TMS320C6678, TMS320C6657

Hello Champs,

C6678 data manual(SPRS691) specifies POR timing before nRESETFULL assertion.

However C6655/57 data manual(SPRS814A) doesn't describe on nPOR for nRESETFULL Reset Timinng in 7.4.7 Reset Electrical Data / Timing.

Hardware Design Guide for KeyStone I Devices(SPRABI2B) instructs as C6678 data manual does.

Do we really need nPOR assertion before nRESETFULL assertion for C6657 as well?

Regards,
Nori Shinozaki

  • 0
    TI__Genius 12065 points

    Nori,

    The power sequencing timing of C6678 and C6657 should be very similar since they are all KeyStone-I devices.

    I think section 7.4.7 in both C6678 and C6657 data manuals are identical. The Hardware Design Guide statements should apply to all KeyStone-I devices.

    And the power sequencing section (7.4.2) in C6678 and C6657 are similar as well.

    May I ask which place in the C6657 data manual describes differently from C6678 or other KeyStone I devices please?

  • 0 in reply to Steven Ji
    TI__Intellectual 2430 points

    Hello, sorry to be late,

    I attached the pages of the both data manuals.

    POR for C6657 keeps high during full reset.

    Regards,

    Nori Shinozaki

  • 0 in reply to Nori Shinozaki
    TI__Genius 12065 points

    Nori,

    Could you please attach the pages again or let us know which figure/page you are referring to please? Thanks.

  • 0 in reply to Steven Ji
    TI__Intellectual 2430 points

    Steven,

    Sorry,

    2311.RESETFULL.zip

    How about this?

    Regards,

    Nori Shinozaki

  • 0 in reply to Nori Shinozaki
    TI__Guru* 84110 points

    Nori-san,

    Please download the latest version of the data manuals from the TMS320C6678 and TMS320C6657 Product Folders. There have been several updates to the C6678 data manual since the 2010 copy that you are referencing.

    The timing diagrams that you copied are for detailing the timing parameters in the associated tables. These diagrams are not intended to deliver all logic or use case examples.

    The timing diagrams in the power sequencing sections are intended to show the required logical patterns for the case of startup of the device, including all power supplies, clocks, and reset signals. These diagrams show that for the power-on case, PORz and RESETFULLz must both be asserted while the power supplies are being initialized, and that PORz must be de-asserted before RESETFULLz is de-asserted.

    Once power has been established and the complete power-on sequencing process has completed, it is then possible to reset the C6657 (or the C6678) by asserting only the RESETFULLz signal. In that case, the PORz signal does not have to be asserted at the same time as RESETFULLz is asserted.

    Regards,
    RandyP

  • 0 in reply to RandyP
    TI__Intellectual 2430 points

    Hello Randy,

    Thank you!

    How about RESETz?

    I read in the Hardware Design Guide(SPRABI2B) in page 9 that the "RESETz should be de-asserted before RESETFULLz".

    Does this mean that RESETz needed to be asserted then  de-asserted before RESETFULLz?

    RESETz needs to be de-asserted before PORz as C6657 Data Manual wrote in Figure 7-1 Core Before IO Power Sequencing in  page 110 and  Figure 7-2 IO Before Core Power Sequencing in page 112.

    Is this correct?

    Best regards

    Nori Shinozaki

  • 0 in reply to Nori Shinozaki
    TI__Guru* 84110 points

    Nori,

    Sorry it took so long, but I just got a clarification recently that will be included in the next KeyStone Hardware Design Guide, concerning RESETz.

    RESETz needs to be pulled low in two situations:

    1. When the power supplies are first being powered on, RESETz must be low until after the 1.8V supply is stable, as shown in the power sequence diagrams in the data manuals.

    2. When you want to do a programmable reset in which some portions of the device can have the reset blocked. Only RESETz needs to be asserted in this case.

    The point of the statement about RESETz being "de-asserted before RESETFULLz" only means that when RESETFULLz goes high, RESETz must already be pulled high. RESETz does not require a low-to-high edge in normal cases of RESETFULLz being asserted.

    Regards,
    RandyP

  • 0 in reply to RandyP
    TI__Intellectual 2430 points

    Hello Randy,

    Thank you for the confirmation.

    This is what we wanted to hear.

    "RESETz does not require a low-to-high edge in normal cases of RESETFULLz being asserted."

    Best regards,

    Nori Shinozaki