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"Sync" instruction

Michi Yama
Guru 10030 points

Hi,

I have one question.

Does C66x devices have "Sync" instruction.

I don't know well regarding DSP instruction. Some risc processor has "Sync" instruction. "Sync" instruction guarantees  the order of memory access.

Does C66x have similar instruction?

My customer would like to evaluate C66x performance. So customer would like to measure the execution time of the functions. Customer thinks to use

the below sequence.

* Read the timer value   --->   * Execute the function    --->   * Read the timer value

But, if the order of  the function instruction and timer read instruction are changed, it is impossible exactly to measure the execution time of the function.

So customer hopes to guarantee the order of instruction never changed.

Does someone have the answer of this question? 

I appreciate your quick reply.

Best regards,

Michi

  • 0
    TI__Guru* 84110 points

    Michi,

    Please explain more about the nature of the function that is to be benchmarked or measured?

    If this function will take 1000's of clock cycles, then the placement of a few instructions will not be likely to affect the results.

    If this function will take 10's of clock cycles, then the accuracy of the benchmark measurement will be misleading due to the pipeline, even if the timer accesses are in the right place.

    There is no "sync" function that I am aware of, but the CPU & Instruction Set Reference Guide is the place to look for all of the instructions and to see what can be done with them. The MFENCE is the closest that I can think of, but it will not specifically do what you are asking for, and its use can again skew the results from being a valid measurement.

    Specifically, the optimizer will rearrange instructions if it finds value in doing that, but there are barriers across which it will not rearrange those instructions. If all instructions to be measured are in a function, and if inlining is not implemented, then those instructions will have completed before the final measurement is taken. Some levels of optimization may try to "improve" on this and might automatically use inlining to get best performance.

    If you need to understand more about the operation of the compiler, then we can move this thread to the E2E Compiler Forum. Please let us know.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Guru 10030 points

    Dear RandyP-san,

    Thank you for your quick reply.

    Please let me know more you said.

    You said "The optimizer will rearrange instructions." .  Is the optimizer included in the Assember? Is it only software solution, no hardware? If it is so,  is it disabled to

    set the level to "off" of the Compiler?

    Also, please let me know the meaning of "inlining". Is it the same meaning of sequential  order ?

    I appreciate your kindly support.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Guru* 84110 points

    Michi-san,

    Your best resource to understand the compiler and optimization is to go to the TI Wiki Pages and search for "c6000 optimization" (no quotes). The page titled "Optimization Techniques for the TI C6000 Compiler" includes application note, workshop, and TI document resources that will explain things much more fully than I could.

    Michi Yama said:

    Is the optimizer included in the Assembler? Is it only software solution, no hardware? If it is so,  is it disabled to set the level to "off" of the Compiler?

    The optimizer and assembler are separate components of the compiler, but they can work together. It is not a clear answer to you to say yes or no.

    The optimizer is software. I am not sure what you ask about with hardware.

    The optimizer can be disabled. The compiler switches are explained in several of the resources from the Wiki article I mentioned above. If you disable the compiler, then C code will not be useful for any evaluation.

    Michi Yama said:
    Also, please let me know the meaning of "inlining". Is it the same meaning of sequential  order ?

    No inlining is not the same as "sequential order".

    Specifically, what is your customer trying to evaluate on the DSP?

    Regards,
    RandyP