Other Parts Discussed in Thread: TMS320C6678
I am working on the design of a new board (medical imaging field), that will incorporate a TMS320C6678. We wish to use NOR flash memory for bootstrap (BOOTMODE:BootDevice=0), and all non-volatile storage. (There is an FPGA in the design too, so this memory will also hold the configuration bitstream for that device, to be delivered serially to the FPGA by the TMS320 during bootstrap.)
Looking at the device data sheet memory summary table (SPRS691C, table 2-2), it appears that each chip select is enabled for a 64Mi space. I can only assume that the addresses specified in that table are byte addresses.
The device itself only pins out EMIFA00 – EMIFA23 (along with 16 data bits) on its EMIF16 bus. The data sheet says that, if 16-bit memory is used for these chip selects, EMIFA23 should connect to the least significant memory device address line. This makes sense to me, as it means that EMIFA00 – EMIFA22 specify a 32-bit object in a space of 2**23 (8Mi) objects, and EMIFA23 is used in that data bus width mode to select the upper or lower 16-bit word for the addressed 32-bit object.
This gives 32MiBytes per chip select, when using a 16-bit parallel memory device, as the footnote says.
Do we then see an alias of each 32MiB block of memory in the CSn spaces?
Also, table 2-2 in SPRS691C identifies EMIF16 data space chip selects as CS2 – CS5. I understand however that a bootstrap using an EMIF16 device must use CE0. The EMIF16 interface pins out EMIFCE0# – EMIFCE3# (table 2-15), and I plan to use these four enables to generate a chip enable and upper two address lines for my 64Mi x 16 NOR flash device.
How are the EMIF16 CS2 – CS5 data spaces in the memory map in table 2-2 related to balls EMIFCE0# – EMIFCE3#?
