AM335x ADC interrupts and FIFO Count

Prateek,

What type of environment are you working on; starterware, linux, android? How are you trying to read the FIFO count; using an API or raw address read?

-Tyler

I am working on Linux and using adc_readl() which again uses readl() to read the FIFO count. Also i want to use only 2 channels but i'll be reading value on them, one after another can; i use all 16 steps for each of them?

Hi Prateek,

Concerning your question about the "Out of Range" interrupt, you should never see a zero count after that interrupt.  There are two possible reasons for this that I can think of:

1. The interrupts are not cleared before they are enabled, so there is a residual interrupt.

2. Are you looking at the correct fifo, since there are 2. The selection is in the step config registers.

We currently do not enable  the "Out of Range" feature in our Software Development Kit, so please post back if you are still having issues.

If you are using 2 channels, you only need two steps.  You can only use one channel per step (single ended) or two channels per step (differential). If you assign two channels (single ended) to one step each, you will read them back one after the other continuously.

You can assign a channel to multiple steps, but the only reason to do that is if you want some out of order capture such as the following example with six steps where4 are assigned to ch0 and two to ch1.

ch0

ch0

ch1

ch0

ch0

ch1 

.

.

.

Hi Jeff,

              Thanks for your reply. I do clear the interrupt before enabling it also i am reading FIFO1 which is set in STEPCONFIG as well.

Apart from that can you please explain me relation between steps and channel as, i am still confused.

my task is to continuously covert analog channel but send the ADC value at which interrupt occurred and values before it (depends on how many are there in FIFO), to user-space only when "out of range interrupt occurs". For which i am enabling all the steps only when read_raw is called after which read call waiting in a wait queue and once interrupt occurs pass the value to user space and disable the steps to stop conversion.

The reason why i want to send whole FIFO to user space is because user-space applies a LPF on those values (because 16 samples average is not enough in this case).

I am facing two problems in it

1. how many steps to enable for each channel?

2. Even after conversion FIFO count is 0?

Probably this will help you identify the something which i am missing.Thanks in advance. please help.

Prateek,

Sorry I was not clear.  

1. You want to allocate 1 to 1: one step per each channel. Any unused steps should be disabled.

2. You want to use continuous capture mode.  Oneshot mode will only get you one sample for each active step. But I believe in either case FIFO count should not be zero.

There is working reference in our Linux SDK05.07: http://processors.wiki.ti.com/index.php/AM335x_ADC_Driver's_Guide

The SDK is found here: http://www.ti.com/tool/linuxezsdk-sitara

Also you can find a baremetal reference project called Starterware with an ADC capture example: http://processors.wiki.ti.com/index.php/StarterWare

Please post back if you can't resolve your issue:  Worst case we can give you a register dump of some working code.

Hi Jeff,

             Thank you for your reply. I tried ADC out of range interrupt and my observation is:

1. I set ADC lower range as 20 & Upper Range as 40, so interrupt should occur only when ADC value is below 20 & above 40, at 20 & 40 (or within range) there shouldn't be any interrupt, but i get an interrupt on 39 sometimes on 38 or 37 as well. I know this because i print all 64 values inside FIFO1 in ISR (before this i disable ADC inside ISR).
2. All 64 values in FIFO1 are same, say for instance all are 38. (I doubt that reason for this can be very fast conversion which is happening there in continuous mode)

Configuration: I configure Only Step 9, FIFO1 and 16 sample average for Channel0 (step enable register REG_SE- 512 decimal) and Step10, FIFO0 and 16 samples average for Channel1(REG_SE - 1024 decimal). I read channels sequentially so  configure them sequentially (One channel at a time).

For Both the steps open delay is 512.

I have following doubts:

1. When i read 64 values in FIFO1, am i reading the value at which interrupt had occurred, & values before it, am i correct? if not please correct me.
2. I still get FIFO1 count as 0 even thought i am able to read the values from FIFO1. What could be the reason of this?
3. What happens when i don't enable FIFO overflow interrupt and FIFO overflows?

Please Note: First i am updating ADC RANGE register (till this everything is diabled), and when i go to read then only i enable ADC, configure the steps (in my case only one either step9 or step2: depends on which channel i am reading), then enable only that step, i do this in same sequence as written.

Please help, Thanks in advance.

Hi Prateek,

Since we do not use the out of range interrupt in our SW, I'm going to need do some further investigation and then I will respond.

Hi Jeff,

          It is really important for us to resolve if there is an issue in ADC driver, Please let me know if i posting adc driver code helps TI to reproduce the issue

i'll. Also i am using the ADC driver in BSP-5.07 and modified it according to requirements. It would be great if we get help

Thanks in advance.

Regards,

Prateek

Hi all,

            If any one has any Idea on posts above, Please help.

Regards,

Prateek