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FPGA interfaced to HPI Port, how fast can I read/write data to HPI? Where is this specifified?

Edward Wronka
Prodigy 20 points

I have a hardware design that has a mode where we do not actually need to run the c5510, BUT we do need some extra memory off of the FPGA it is connected to.

The HPI port can make the internal memory of the DSP look like SRAM. That is how we bootload it.

My question is, how fast can I read and write to this memory. There are so many documents related to the c5510 DSP, where is the speed of this interface even specified?

  • 0 in reply to pathfinder
    Prodigy 20 points

    This application note is pretty close to what I was looking for, but I actually want to use the HPI port in non-multiplexed mode which is left out of this app note for some reason.

    From looking at the data sheet----if you look at the stated timing, E2 (data valid time) is 80 ns if the part is running at 200 MHz. I was hoping it would be faster. Look at timing diagram on the next page (page 80).

     

    Table 5−34. EHPI Switching Characteristics

    VC5510/5510A-160

    NO. PARAMETER

    VC5510/5510A-200 MIN MAX

    UNIT

    E1 td(HDSL-HDD)M Delay time, HDS low to HD bus read data driven (memory access) 6 16 ns

    E2 td(HDSL-HDV1)M Delay time, HDS low to HD bus read data valid (memory access) 14P+10†‡ ns

    E4 td(HDSL-HDD)R Delay time, HDS low to HD bus read data driven (register access) 6 16 ns

    E5 td(HDSL-HDV)R Delay time, HDS low to HD bus read data valid (register access) 16 ns

    E6 tdis(HDSH-HDIV) Disable time, HDS high to HD bus read data invalid 6 16 ns

    E7 td(HDSL-HRDYL) Delay time, HDS low to HRDY low (during reads) P+10† ns

    E8 td(HDV-HRDYH) Delay time, HD bus valid to HRDY high (during reads) 2 ns

    E9 td(HDSH-HRDYL) Delay time, HDS high to HRDY low (during writes) 16 ns

    E10 td(HDSH-HRDYH) Delay time, HDS high to HRDY high (during writes) 14P+10† ns

    † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

    ‡ EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination