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EDMA Priority Queue Length

Aaron Hershberger
Prodigy 50 points

I noticed in an earlier post the ability to customize the three queue lengths within a particular priority with the limit that the sum must be =< 16.(SPRA994)  My question is whether each queue type isn't limited to being =< 7.  It looks like the register for setting the three types only uses three bits per type so values could range between 0-7 and you couldn't, for example, set the EDMA queue to 0, the TR queue to 1, and the L2/QDMA queue to 15.

 

I'm wanting to enqueue 8 QDMA requests at once so this appears to be my issue.  This is all on a C64XX.

 

Thanks

  • 0
    TI__Guru* 84110 points

    Aaron,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages.It looks like you have already started to search those for helpful information and to browse for the questions others may have asked on similar topics.

    Which C64xx device are you using? Resource issues can vary from one device to another.

    It can be helpful to reference any specific posts that you are asking about. This is for the case of specific issues that may be different from our understanding of your current question.

    You seem to have a good understanding of the C64xx EDMA queue allocation. I am not sure what your question is.

    You can use QDMA with different priority levels to use different queues to reach a total in-flight QDMA request count > 7.

    Since the transfers will happen serially anyway, would it work for your application to use DMA channels that you can start at the same time, or that can chain from one channel to the next?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 50 points

    Hi Randy,

     

    We're using a C6416.  My question was whether or not you can in practice set queue lengths greater than 7.  This confusion was based on SPRU610C that seems to imply that only three bits are used to denote the L2 queue length.

    I probably could used a chained EDMA operation; I just happened to used a QDMA on my first cut through the code.  I've always like QDMA better for some reason.

    Thanks,

    Aaron

     

    BTW, TI has one of the better forums hosted by an IC vendor, so kudos for that.

  • 0 in reply to Aaron Hershberger
    TI__Guru* 84110 points

    Aaron,

    Anytime our technical documentation leaves something as "implied", we probably need to improve that documentation.

    But 3 bits means just 3 bits. I remember an example showing how you could do 7 + 7 + 2 = 16, because each of the types can only go up to 7.

    So, is it adequate for your application to use two different priority queues for the 8 QDMA transfers?

    Thanks for the kind words on the forum, which I will pass on to our hosting team. We try to make it good by doing what we can; the E2E forum will be great when we get more engineers like yourself who have gained experience and y'all start providing your vision and insight as answers here for the newbies.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 50 points

    Randy,

     

    Yes I think I can break the 8 into two different priorities since I really don't need long queue lengths for anything else. 

     

    Just to confirm, I should use a higher priority on the first 4 and then a lower priority on the second 4 to ensure that they are executed serially?

     

    Thanks,

    Aaron

  • 0 in reply to Aaron Hershberger
    TI__Guru* 84110 points

    Aaron,

    It has been a long time since I used the EDMA in the C6416 devices, so I would only be able to repeat what you have read in the User Guide.

    Does it specifically say that all transfers queued up in one queue will be executed before any in a lower priority queue?

    If it does not say that, then I would not count on it. Two ways to guarantee the order are to have them in the same queue or to chain them as DMA channels.

    Regards,
    RandyP

  • 0 in reply to RandyP
    TI__Guru* 84110 points

    Aaron,

    In the TMS320C64x EDMA Architecture App Report SPRA994, Section 2.4 on page 6 says

    "Only one TR from each priority queue can be serviced at a time by the address generation/transfer logic. The transfer logic can process transfers of different priorities concurrently."

    This means that if you put 4 QDMAs 1-4 into High Q1 and 4 QDMAs 5-8 into Medium Q2, they will possible execute 1 & 5, then 2 & 6, and so on, depending on the respective details of the 8 transfers.

    If you want to discuss some of the details of your order-dependencies, we can make some other suggestions. For example, you could have some of the QDMA transfers chain to an EDMA transfer when that QDMA has completed.

    Or, with the QDMA depth set to 7, just go ahead and submit 8 requests. The depth is for the Queue and not for the entire EDMA module. So by the time you have written 7 requests into the Medium Q2, for example, the first one should be starting to be serviced and will be pulled out of Q2. This leaves room for the 8th request to get into Q2 without causing a stall. This plan works best if no other DMA requests will go to Q2, because if any others are in there, then the Queue could get backed up and your last QDMA might get stalled and block requests going to all of the queues, which could be bad.

    Be sure to check the C6416 errata document to see if there are any issues with queues filling.

    Please let us know if we can help any.

    Regards,
    RandyP