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About DM368 SPI data transfer

g.f.
Guru 15520 points

Hi,

I have a question about DM368 SPI.

We are using SPI to configure FPGA from DM368.
So, DM368 is master of SPI and FPGA is slave.

When sending data from DM368 to FPGA, after sending 1KB data,
it stops for a while. Then after a while, it restarts data transfer.
Is there any data size limitation in DM368 SPI transfer?

My understanding is that there are no size limitation for transmit,
so you can transfer data sequentially with any data size.

best regards,
g.f.

  • 0
    Guru 15520 points

    Hi,

    I change my question.

    After sending 1KB data have been completed through SPI,
    DM368(SPI Master) outputs SPI CLK for 8 cycle  but there are no data transfer during this period.

    I think if SPI finish data transfer, SPI CLK will stop too.

    I searched for the reason why DM368 outputs SPI CLK for 8 cycle which is not meant.
    I found out that if CSHOLD was set to '1' it output SPI CLK,
    but if CSHOLD was set to '0' it didn't output SPI CLK.
    In addition, CSHOLD is set up after 1KB data transfer.

    Does CSHOLD affect to SPI CLK output?

    best regards,
    g.f.