AM335x GPMC Asynchronous Single Write Access

Daisuke Maeda

Guru 20245 points

About the data hold time, while CSn is asserted, is it extended?

AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. H)
http://www.ti.com/lit/ug/spruh73h/spruh73h.pdf
7.1.4.1.5 GPMC Configuration for Asynchronous Single Write Access (Page 361)

Best regards,

Daisuke

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Yes Daisuke, it's extended by 1 cycle. See the timing diagram on next page.

0 Daisuke Maeda over 12 years ago in reply to Biser Gatchev-XID

Guru 20245 points

Hi Biser,

Thank you for your reply.

In Figure 7-50 the data hold time (valid data) is 1 cycle.
Does not it depend on the CSn assertion period after WEn de-assertion?
If the CSn assertion period after WEn de-assertion is n cycles, is it n cycles?

Best regards,

Daisuke

0 Biser Gatchev-XID over 12 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

For asynchronous single write access, write cycle time is WrCycleTime = WeOffTime + AccessCompletion = WeOffTime + 1. For the AccesCompletion, the GPMC requires 1 cycle of data hold time (CSn deassertion). (TRM page 361)

0 Daisuke Maeda over 12 years ago in reply to Biser Gatchev-XID

Guru 20245 points

Hi Biser,

Thank you for your reply.

I understand it as follows.

- Data hold time (WEn de-assertion to DATA invalid) is 1 cycle.

- WrCycleTime must be "WeOffTime + 1" cycles.

- CE output hold time (WEn de-assertion to CEn de-assertion) is 1 cycle.

- CsWrOffTime must be "WeOffTime + 1" cycles.

Is my understanding correct?

Best regards,

Daisuke

0 Biser Gatchev-XID over 12 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

Yes, I think so.

0 Daisuke Maeda over 12 years ago in reply to Biser Gatchev-XID

Guru 20245 points

Hi Biser,

Thank you for your reply.

Best regards,

Daisuke

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AM335x GPMC Asynchronous Single Write Access