Generating Keystone SDRAM VTT REF

David,

We are in the process of updating the Hardware Design Guide. The new version currently includes the following sections:

2.2.5.1 VTT Termination Supply

The DDR3 interface requires a VTT termination at the end of the flyby chain for the DDR3 address and control signals. The 0.75V termination voltage is generated using a special push/pull termination regulator specifically designed to meet the VTT requirements for DDR3. The Texas Instruments TPS51200 is one device that meets these requirements. Although the VTT supply is not connected to the KeyStone I devices it is necessary for the DDR3 interface connected to the device.

2.2.5.2 VREF Supply

The C66x device requires a 0.75V reference voltage for the DDR3 SDRAM interface connected to the VREFSSTL pin. Many VTT termination supplies will provide a separate supply output pin specifically for a reference voltage. This is true for the TPS51200 which provides the reference voltage on the REFOUT pin. If the reference voltage is provided by the VTT termination supply, it should be connected to the VREFSSTL pin. If it is not supplied, a simple voltage divider as illustrated in Figure 4 can be used. All resistive components must be 1% or better tolerance. The components in the following figure must be placed close to the respective device pin. If a resistor divider is used the VREFSSTL source voltage MUST be generated from the same supply as the DRAM interface to the device (DVDD15). Both must track in parallel as the supply voltage fluctuates.

Does this help? Does it address your concerns?

Regards,
RandyP

Thanks for the response, Randy.

I'm a bit confused by: "The components in the following figure must be placed close to the respective device pin."

The VREFSSTL net would need to feed pins on the Keystone device, all SDRAMs, and the VREF input on the TPS51200 (needed to generate VTT by tracking DVDD15). On both eval platforms I originally mentioned, VREFSSTL is a long copper route with the voltage divider located at one end of the net near the first SDRAM.

I don't know how to reconcile the above statement with the fact that the VREFSSTL net essentially needs connect to several devices.

This also leads to the obvious question...which is the best topology:

1. Use REFOUT pin on TPS51200 to feed VREF inputs on SDRAMs and Keystone; voltage divider only feeds TPS51200 REFIN (used on neither TI eval platform but implemented on other non-TI eval platforms).

2. Use a separate voltage divider for a) TPS51200 REFIN input and b) VREF inputs on other devices (C6678 eval platform).

3. Use a single voltage divider to feed everything (C6657 eval platform).