capture on custom DM8168 with fpga

XUEBIN WEN1

Other Parts Discussed in Thread: TVP5150

hello!

when i capture vip0 on our custom dm8168, at DQ first frame it appera error "V4L2_BUF_FLAG_ERROR present!!! Port a overflowed!" why?

our psp verson is EZSDK 5.03,int bootscript, use "firmware_loader $HDVPSS_ID /usr/share/ti/ti-media-controller-utils/dm816x_hdvpss_v4l2.xem3 start " instead "firmware_loader $HDVPSS_ID /usr/share/ti/ti-media-controller-utils/dm816x_hdvpss.xem3 start",

over 12 years ago

0 Brijesh Jadav over 12 years ago

TI__Guru**** 476575 points

Hi,

This means VIP is overflowed and you will have to reset the port. Please check the sample application to know how to reset port.

There could be multiple reasons for the overflow. Can you explain how Vip path is used? What is V4L2 configuration you are using?

Regards,

Brijesh Jadav

0 XUEBIN WEN1 over 12 years ago in reply to Brijesh Jadav

Intellectual 395 points

thanks for your reply, i am work use EZSDK5.03 i modify files includes arch/arm/mach-omap2/ti81xxfb.c and driver/media/video/ti81xxvin_main.c

0 XUEBIN WEN1 over 12 years ago in reply to XUEBIN WEN1

Intellectual 395 points

int ti81xxvin_main.c

modify from "for (i = 0; i < 1; i++) " to " for (i = 0; i < 2; i++) " , and comment some v4l2_subdev call

we use fpga instead of 7002 signal to vip0 and 5150 signal to vip1

in tvp5150.c i use tvp5150_write(sd, TVP5150_MISC_CTL, 0x09), to enable YCrCb OUTPUT then 5150 can sent embedded 8bit data , i can captute it with vip1_b

on vip0, fpga signal discrete 24 RGB data with HSYNC/VSYNC/ACTIVD/PLCK, if i start app capture before fpga sinal, uart printf "VPSS creat fail" and if i start capture after fpga sinal, when capture first fram uart printf "V4L2_BUF_FLAG_ERROR present!!! Port a overflowed",

someone tell me 1.1version have problem on capture discrete sync, realy?

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capture on custom DM8168 with fpga