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OMAP3530 EVM Clock Questions and gel files

Sean Bedford
Expert 1560 points
Other Parts Discussed in Thread: OMAP3530

Good afternoon,

We have just got a OMAP35x EVM board to evaluate.  I have it running in CCSv5 using a XDS510 USB with the omap3530 gel files.

I have a couple of questions fistly in the Gel files it sets the system clock as 19.2MHz but the clock on the board is 26MHz so is this incorrect in the Gel file?  I have changed it and it does not effect the small bench mark program I am running therefor I assume it aslso does not change the clock speed of the processor so what is it doing?

Secondly by decault the processor clock seems to be set as 330MHz.  I want to run it at 720MHz.  So I started by halfing the DPLL_DIV_VALUE divider and then doubling the nL3Div divider to keep the L3 clock at at 166MHz.  This stops it working, the program is loaded but with this error in the console

"Cortex_A8_0: Trouble Setting Breakpoint with the Action "Finish Auto Run" at 0x8005baf4: Error 0x20000008/-1066 Severe Error during: Break Point,  Cannot set/verify breakpoint at 0x8005BAF4"

it does not jump to main as usual and seems to be disconnected from the device ("disconect from device" in run menu is grayed out), when I click connect it gives the following error

"Error connecting to the target: Error 0x80000244/-1178 Fatal Error during: Register, Initialization, OCS, The target does not have a CPU clock. ".

This is the info printed when the modified Gel file is loaded:

Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable
Cortex_A8_0: GEL Output:  Putting DPLL into bypass before proceeding
Cortex_A8_0: GEL Output:  Putting CORE DPLL into bypass before proceeding
Cortex_A8_0: GEL Output:  Locking CORE DPLL
Cortex_A8_0: GEL Output:  PRCM clock configuration IIA setup has been completed
Cortex_A8_0: GEL Output:  SystemClock = 19.2 MHz
Cortex_A8_0: GEL Output:  DPLL_MULT_VALUE = 242
Cortex_A8_0: GEL Output:  DPLL_DIV_VALUE = 6
Cortex_A8_0: GEL Output:  CORE_DPLL_CLK = 1327.542 MHz
Cortex_A8_0: GEL Output:  CORE_CLK = 663.771 MHz
Cortex_A8_0: GEL Output:  L3_CLK = 165.9427 MHz
Cortex_A8_0: GEL Output: MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks
Cortex_A8_0: GEL Output: common_sdram_init() completed
Cortex_A8_0: GEL Output: SDRC initilization for mDDR_Samsung_K4X51323PC completed
Cortex_A8_0: GEL Output: 19.2MHz clock configuration IIa
Cortex_A8_0: GEL Output:  CORTEXA8_CORE_VERSION = 0x411FC083
Cortex_A8_0: GEL Output: Target contains version r1p3 of the CortexA8...
Cortex_A8_0: GEL Output: Read the ETM_POWER_DOWN_STATUS register...
Cortex_A8_0: GEL Output:  ETM_POWER_DOWN_STATUS = 0x00000001
Cortex_A8_0: GEL Output: ETM Access is enabled!
Cortex_A8_0: GEL Output: ETM_ID = 0x410CF232
Cortex_A8_0: GEL Output: ETM Version is: 3.3v2
Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable
Cortex_A8_0: GEL Output:  Putting DPLL into bypass before proceeding
Cortex_A8_0: GEL Output:  Putting CORE DPLL into bypass before proceeding
Cortex_A8_0: GEL Output:  Locking CORE DPLL
Cortex_A8_0: GEL Output:  PRCM clock configuration IIA setup has been completed
Cortex_A8_0: GEL Output:  SystemClock = 19.2 MHz
Cortex_A8_0: GEL Output:  DPLL_MULT_VALUE = 242
Cortex_A8_0: GEL Output:  DPLL_DIV_VALUE = 6
Cortex_A8_0: GEL Output:  CORE_DPLL_CLK = 1327.542 MHz
Cortex_A8_0: GEL Output:  CORE_CLK = 663.771 MHz
Cortex_A8_0: GEL Output:  L3_CLK = 165.9427 MHz
Cortex_A8_0: GEL Output: System Reset has occured.

Can anybody suggest what I am doing wrong in changing the CPU frequency of the ARM and why changing he clock from 19.2MHz (which I belive is wrong) to 26MHz has no effect?

Many thanks

Sean

  • 0
    TI__Guru 65405 points

    Hi Sean,

    Could you attach the gel file which you are using?

    The clock from 19.2 MHz is allowed. What clock source you are using - crystal oscillator or CMOS digital clock because main input clock could one of both. Crystal oscillator clock could be (only at 12, 13, 16.8, or 19.2 MHz) or CMOS digital clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz).

    An other way to read and manage the system frequency is via console. Go to /sys/devices/system/cpu/cpu0/cpufreq and check cpuinfo_cur_freq.

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Expert 1560 points

    Hi Tsvetolin,

    I have attached the Gel file.  It is one that is installed with CCSv5.3 only I have changed the calls to "SelectSysClock_19_2MHz();" to call "SelectSysClock_26MHz();" and the memory setup to the micron memory to suit the OMAP35x EVM board.

    I now that you can use those values for the clock and I now that here is a 26MHz clock on the EVM board but I have a benchmark program I am timeing and my question is why when I use the default files with the clock set wrongly to 19.2MHz I get the same results as when I have changed it to 26MHz?

    This seems to show that setting the input clock has no effect on the speed of the processor which cant be right?

    please read on the the next post with a different file attached.

    omap3530_cortexA.gel
  • 0 in reply to Sean Bedford
    Expert 1560 points

    The file attached to this post is also installed with CCSv5.3 un edited it works and the gel output indicates the clock is setup at 330MHz (as in my original post).  Attached is my edited file where I have changed the following

    • line  121, nL3Div = 4; instead of 3 to keep the L3 clock at 166MHz.
    • line 634, DPLL_DIV_VALUE = 12 instead of 25 so the MPU clock is 660MHz.

    The Gel output then becomes:

    Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable
    Cortex_A8_0: GEL Output:  Putting DPLL into bypass before proceeding
    Cortex_A8_0: GEL Output:  Putting CORE DPLL into bypass before proceeding
    Cortex_A8_0: GEL Output:  Locking CORE DPLL
    Cortex_A8_0: GEL Output:  PRCM clock configuration IIA setup has been completed
    Cortex_A8_0: GEL Output:  SystemClock = 26.0 MHz
    Cortex_A8_0: GEL Output:  DPLL_MULT_VALUE = 332
    Cortex_A8_0: GEL Output:  DPLL_DIV_VALUE = 12
    Cortex_A8_0: GEL Output:  CORE_DPLL_CLK = 1328.0 MHz
    Cortex_A8_0: GEL Output:  CORE_CLK = 664.0 MHz
    Cortex_A8_0: GEL Output:  L3_CLK = 166.0 MHz
    Cortex_A8_0: GEL Output: MM02: mDDR Micron MT46HM32LFCM - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks
    Cortex_A8_0: GEL Output: common_sdram_init() completed
    Cortex_A8_0: GEL Output: SDRC initilization for mDDR_Micron_MT46HM32LFCM completed
    Cortex_A8_0: GEL Output: 19.2MHz clock configuration IIa
    Cortex_A8_0: GEL Output:  CORTEXA8_CORE_VERSION = 0x411FC083
    Cortex_A8_0: GEL Output: Target contains version r1p3 of the CortexA8...
    Cortex_A8_0: GEL Output: Read the ETM_POWER_DOWN_STATUS register...
    Cortex_A8_0: GEL Output:  ETM_POWER_DOWN_STATUS = 0x00000001
    Cortex_A8_0: GEL Output: ETM Access is enabled!
    Cortex_A8_0: GEL Output: ETM_ID = 0x410CF232
    Cortex_A8_0: GEL Output: ETM Version is: 3.3v2
    Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable
    Cortex_A8_0: GEL Output:  Putting DPLL into bypass before proceeding
    Cortex_A8_0: GEL Output:  Putting CORE DPLL into bypass before proceeding
    Cortex_A8_0: GEL Output:  Locking CORE DPLL
    Cortex_A8_0: GEL Output:  PRCM clock configuration IIA setup has been completed
    Cortex_A8_0: GEL Output:  SystemClock = 26.0 MHz
    Cortex_A8_0: GEL Output:  DPLL_MULT_VALUE = 332
    Cortex_A8_0: GEL Output:  DPLL_DIV_VALUE = 12
    Cortex_A8_0: GEL Output:  CORE_DPLL_CLK = 1328.0 MHz
    Cortex_A8_0: GEL Output:  CORE_CLK = 664.0 MHz
    Cortex_A8_0: GEL Output:  L3_CLK = 166.0 MHz
    Cortex_A8_0: GEL Output: System Reset has occured.

    Suggesting that what I am attempting to do is correct (ie the memory clock is still 166 and he CPU clock is 664).  However rather than jumping to main it does the below:

    From here clicking run does nothing and nothing works as it should.

    Can you please tell me what I am doing wrong?

    Many thanks

    Sean

    omap3530_cortexA.gel
  • 0 in reply to Sean Bedford
    Expert 1560 points

    Good afternoon,

    I am still stuck on this could somebody please clarify the clocks for me, what is the differance between the MPU clock and the core clock?  Which one is the clock speed of the ARM processor?

    Is there any way to clarify what the speed of the actual ARM core is?

    Regards

    Sean