how to use L2S"ram" efficiently

Hi Hongmei

Actually my target is to run HD transcoder on dsp

on single core running Hd decoder and encoder seems to be an horrible nightmare to me.

so i decided to run do the configuration of decoder and encoder such that decoder and encoder in different core.

got answer for l2Sram, i think i should give up single core running Hd decoder and encoder

thanks

Anshul

Hi Anshul,

You are right, we cannot achieve real-time HD transcoding using a single C6678 core. If you are using C6678 H264HP decoder, please note that the multi-core task split is now for 2 cores only.  

Thanks,

Hongmei

HI Hongmei

to run transcoder for small resolution, i called the encoder create and process function, just below the decoder with some memory tweaking

but i found whatever tweaking, i have done for giving memory has degraded performance (fps < 20  only work with real time)   ,

and over there decoder is running on single core and encoder on 8 core, memory for intercommunication is DDR (for time shake).

also I am not too much comfortable with sysbios semaphore and syncronisation.

so can you guide from start (  :)  ) . like how to make this possible.

Hi Anshul,

What dataIO are you using for your application? Is it through PCIe, or TFTP, or something else?

Thanks,

Hongmei

hi hongmei

i am using PCIe

i was removing dependency of decoder on core 0.

and i did change

mcViddecParams.core_task_ID  = (cxt->coreId == 0)?IVIDMC_TASK_MASTER:IVIDMC_TASK_SLAVE;

mcViddecParams.core_task_ID  = (cxt->coreId == 3)?IVIDMC_TASK_MASTER:IVIDMC_TASK_SLAVE;

but still decoder is not running if i am not passing argument 0 in core team mapping, then it do not work..

what else changes are requird to make it work.

File = siu/vct/siuVctDecode_xdm1p0.c + 247 in latest mcsdk release

thanks

anshul

Hi Anshul,

Can you please give us more details about the end goal of your application?

What codec will be used? What is the stream type (e.g., BP or HP for H264)? What is the resolution (e.g., 720p or 1080p or something else)? What bit rate will be used? Please provide answers to these questions for both decoding and encoding.

Thanks,

Hongmei

Hi

I need HD 1080p resolution with 60 fps

so i was going with HP H264 decoder because BP dont support that high resolution

i was using HP H264 encoder since i found that using configParam.cfg that work for both hp and baseline, so go with hp encoder

atually on intel xeon 15 channel (hd) work easily and i want to show the capability of c6678 so my end goal was to achieve 15Channel

for now i but want them to belive that even hd trans coding is possible, with that i can buy time and emulator to achive 15 channel.

thanks

Anshul

Hi Anshul,

Thanks for the information. Can you please confirm if the following is what you are trying to achieve?

15 channels of transcoding on Advantech DSPC-8681. For each channel of transcoding, you want to do:

1080p60 H264BP decoding (using H264HP decoder) + 1080p60 H264BP encoding (using H264HP encodier)

Is 60fps a must-meet requirement for both the decoding and encoding? Is 30fps acceptable for your application?

Thanks,

Hongmei

hi Hongmei

you are correct that is all what i want to do. that is my end requirement

30fps is ok.

i have achived single  channel d1 input and 3 channel output of cif, qcif and D1 with customizable bit rate.

To achieve end goal my approach was to first  remove the hardcoding of master core0 in ti's sv04 example.

I am looking in sv01 and test application of decoder for reference , still unable to achieve ,might some part is still hardcoded

thanks

anshul

Hi

I feel like, i got answer of my question previously i posted a code snippet

mcViddecParams.core_task_ID  = (cxt->coreId == 0)?IVIDMC_TASK_MASTER:IVIDMC_TASK_SLAVE;

mcViddecParams.core_task_ID  = (cxt->coreId == 3)?IVIDMC_TASK_MASTER:IVIDMC_TASK_SLAVE;

i found that i want to run encoder i need to add one more parameter cxt->coreId

cxt->enc_coreId

cxt->dec_coreId

some thing like that

thanks

anshul

Hi Anshul,

For 1080p30 BP decoding, 2 cores are needed. For 1080p30 BP encoding, 4 or 5 cores are needed. As each C6678 chip has 8 cores, it can support 1 channel of 1080p30 BP transcoding. Advantech DSPC-8681 has four C6678 chips, and therefore it can run 4 channels of 1080p30 BP transcoding.

Thanks,

Hongmei

hi tushar

Got your point but i think that is not enough, it is getting failed at software barrier,

for software  barrier , i think i should start new forum,

this post has got diverted from my original question

to mine end goal. : (

thanks

anshul