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C6678 power up sequence. CVDD1 leakage onto DVDD15.

Simon Pack
Expert 1660 points

On my C6678 design, I follow the recommended power up sequence (core before IO) as given in SPRS691C page 114.

I notice that as my CVDD1 rail ramps up, it pre-biases the DVDD15 rail to around 600mV before the DVDD15 rail is turned on.

The DSP is held in POR during power ramping, and it does not drive out any voltages onto its DDR pins.

I am thinking that there may be a leakage path between CVDD1 and DVDD15 within the DSP itself. Has this been observed before, and will this leakage path damage the DSP ?

Cheers,

Simon

 

  • 0
    TI__Mastermind 46460 points

    Simon,

    Please review the design for another leakage path.  We do not have a known leakage path from CVDD1 into DVDD15.  There is a known leakage path from VDDT into VDDR that is known and characterized.  Please refer to Usage Note 18 in the C6678 Errata document SPRZ334.

    Tom