Other Parts Discussed in Thread: AM3352
Hello,
I'm using AM3352.
I have a question about THRI timing of UART.
For DE controle of RS485 ,I would like to apply interruption in the timing of the completion of transmitting of serial communication in serial driver.
So I set SCR [3] TXEMPTYCTLIT = 1: THR interrupt is generated when TX FIFO and TX shift register are empty.
However, THRI has occurred at the time of a transmitting start.
Is there any factor considered by something?
Thank you,
Hakun
