TMS320C5535 System Clock

YILMAZ KIRÇİÇEK

Intellectual 905 points

Other Parts Discussed in Thread: TMS320C5535

Hi all,

I want to use TMS320C5535 in a timing critical project. But I am not familiar with TMS320C5535.

First I have looked that TMS320C5535 does not have external clock input for the timers module.

So I decide to provide 2.5ppm (maybe 1 ppm) 12Mhz clock signal to TMS320C5535.

But I could not able to find any data regarding the PLL unit and internal timing accuracy.

Required speed is 100Mhz and accuracy is 5ppm. (Including temperature, aging, supply etc.)

Is it possible for TMS320C5535 ? (10ns tcy with 5ppm accuracy)

Is CLKOUT pin frequency exactly same with the system clock ?

Best regards.

over 12 years ago

0 Steve Tsang over 12 years ago

TI__Mastermind 23785 points

The internal system clock can be an external clock source coming in via CLKIN pin and PLL bypass or using the PLL to program the internal clock. If you need a very precise clock, you can use the CLKIN to source it. CLKOUT is for debug purpose to monitor internal clocks. You can refer to CCSSR register for details. As for CCSSR selection like 0h, 2h, 4h, 6h, 8h, Ah, Ch and Eh, it is looking at the output of the Clock Generator at the LS, not PLLOUT.

Hope this help.

Regards.

0 YILMAZ KIRÇİÇEK over 12 years ago in reply to Steve Tsang

Intellectual 905 points

Hi Mr. Tsang,

I thank you for your response. But I want to be sure about pll and clkout accuracy.

I have read the "Table 1-6. PLL Output Frequency Configuration" section on SPRUH87C and

see that it easy to set system clock to 100 Mhz with 12Mhz external clock.

(RDBYPASS=0, OUTDIVEN=0, RDRATIO=512, M=4296)

Will the system clock be 2.5ppm when I apply 2.5ppm ext. clock ?

Best regards.

0 Steve Esposito over 12 years ago in reply to YILMAZ KIRÇİÇEK

Prodigy 30 points

Hi:

I am also very interested in this subject. While the timing of my application is not as critical as outlined above, the system clock is the time base for everything, and I am wondering if it is as accurate as the crystal. On our case, we use a 20 ppm crystal and we would be thrilled with a 20 ppm system clock after being multiplied by the PLL.

We raise this question because we question the accuracy of our timer, that is clocked from the system clock at 12.288 MHz.

If anyone with an understanding of the accuracy of the system clock when using the PLL, it would be great to hear their input.

Thanks,

Steve

0 Steve Tsang over 12 years ago in reply to Steve Esposito

TI__Mastermind 23785 points

Steve,

We had taken some data on this and posted here. Hopefully this give you some insight.

Regards.

0 Steve Esposito over 12 years ago in reply to Steve Tsang

Prodigy 30 points

Steve:

Thank you very much for your input on this important issue. For some reason, I can't seem to find where you posted the data? Could you please point me in the correct direction.

Thanks,

Steve

0 YILMAZ KIRÇİÇEK over 12 years ago in reply to Steve Esposito

Intellectual 905 points

Hi,

Am I missing something ?

Where is the posted data ?

Best regards.

0 Steve Tsang over 12 years ago in reply to YILMAZ KIRÇİÇEK

TI__Mastermind 23785 points

This is the link.

http://e2e.ti.com/support/dsp/c5000/f/109/p/225735/801214.aspx

Regards.

0 YILMAZ KIRÇİÇEK over 12 years ago in reply to Steve Tsang

Intellectual 905 points

Hi Mr. Tsang,

I thank you for your response. But I want to be sure about pll and clkout accuracy.

Advices, explanations and solutions given in the link is about the correct PLL settings.

I have read the "Table 1-6. PLL Output Frequency Configuration" section on SPRUH87C and

see that it easy to set system clock to 100 Mhz with 12Mhz external clock.

(RDBYPASS=0, OUTDIVEN=0, RDRATIO=512, M=4296)

Will the system clock accuracy be 2.5ppm when I apply 2.5ppm ext. clock ?

Best regards.

0 Steve Tsang over 12 years ago in reply to YILMAZ KIRÇİÇEK

TI__Mastermind 23785 points

If you use thePLL bypass mode, internal system clock will be same as external clock source. Otherwise, it will be the output of PLL and subjects to PLL's jitter.

Regards.

0 YILMAZ KIRÇİÇEK over 12 years ago in reply to Steve Tsang

Intellectual 905 points

Hi Mr. Tsang,

I thank you for your response.

According to the datasheet of TMS320C5535, maximum allowed clock input frequency is 24 MHz.

(This can require a little bit more attention for bootlader.)

And this speed is not enogh if we do not use PLL (bypass mode)

So last question is regarding PLL jitter,

What is the PLL jitter level ? (with clean power supply)

We do not need to know exact value. Please just give us a rough idea, 5ppm is achievable or not ?

Best regards.

0 Steve Tsang over 12 years ago in reply to YILMAZ KIRÇİÇEK

TI__Mastermind 23785 points

First, I want to note that the PLL input range is spec'ed at 32.768kHz-170kHz max. This is done by the Reference Divider.

Next is the PLL jitter, internal data shows this PLL jitter is well bounded at less than 200ps at the frequency range of 100MHz-200MHz. C5535 max frequency is 100MHz. I don't have this jitter in PPM.

Hope this help.

Regards.

0 YILMAZ KIRÇİÇEK over 12 years ago in reply to Steve Tsang

Intellectual 905 points

Hi,

Our target tcy is 10ns and 200ps jitter is too high for 10ns signal.

I will solve the timing critical issues with external circuitry.

So I have to check that if C5535 external interrupt latency is deterministic or not.

Best Regards.

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TMS320C5535 System Clock