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Keystone Bootloader: RBL DDR3 configuration. Leveling?

Ricardo Martinez
Intellectual 290 points

Dear all,

I'm using C6670 EVM. I'm loading my application into DDR3 using Ethernet RBL (ROM Boot Loader). I am not using I2C Intermediate Boot Loader.. So, my board is properly configured for Ethernet boot and everything works as expected.

However, I'm worried about the following: DDR3 configuration by RBL does not include leveling configuration (read or write leveling). I have checked this in Table 2-3 "DDR configuration" in Keystone Architecture Bootloader User Guide (SPRUGY5B). RBL writes into DDR3 PLL configuration, SDRAM Config Register, Timing, PHY CTL, etc, but not into Leveling configuration.

Without leveling configuration, I think that RBL access to DDR3 might not be reliable. One easy solution for this would be slowering down DDR3 clock frequency by PLL configuration. Slow access to DDR3 might not need leveling. However, when I configure DDR3 PLL to 400MHz (this means DDR3-800 access, while default configuration for EVMC6670 is DDR3-1333), RBL can't write to DDR3. So my application won't work. Any DDR3 PLL frequency below default configuration (666.67MHz) won't work. I am updating also timing parameters for the new frequency values without success.

I'm writting the following boot table section into my application binary.

00 00 00 70 00 8F 35 00 02 42 80 F5 00 00 00 00 00 00 00 14 00 00 00 02
63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

According to "tiboot_c66x.h" (because Table 2-3 in SPRUGY5B has an errata), those 3 words in bold above are for DDR3 PLL configuration. That configuration above works perfectly (again, without leveling so I don't truts it to work 100% of the booting processes). 0x14 == 20 (multiplier). 0x2 (dividier). 66.67MHz x 20 / 2 = 666.67MHz appropiate for DDR3-1333 operation.

Changing DDR3 configuration into DDR3-800 (400MHz clk):

00 00 00 70 00 8F 35 00 02 42 80 F5 00 00 00 00 00 00 00 0C 00 00 00 02
63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Above configuration won't work.

Please note that I can configure DDR3 PLL to 400MHz with Emulator editing GEL files and it works properly.

To summarize:

1) I'm worried about lack of DDR3 leveling configuration in RBL

2) I don't understand why I can't configure DDR3 PLL to 400MHz using RBL (indeed, any value below 666.67MHz won't work). I think this could be a feasible solution for the problem in 1).

Thanks in advance.

Regards,

Ricardo

 

 

 

 

 

  • 0
    TI__Expert 6815 points

    Hi Ricardo,

    I am looking into it. I will have an answer for you in the next couple of days.

  • 0
    TI__Expert 6815 points

    Ricardo,

    Ricardo Martinez said:
    So, my board is properly configured for Ethernet boot and everything works as expected.

    By this, do you mean you are able to successfully load the application and execute from DDR?

  • 0
    TI__Expert 6815 points

    A few more things:

    1. Boot table section at 666.67 MHz

    Ricardo Martinez said:
    00 00 00 70 00 8F 35 00 02 42 80 F5 00 00 00 00 00 00 00 14 00 00 00 02
    63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

    What does the highlighted portion (yellow) stand for? I am sorry, but I am not a bootROM expert. The PLL config should start at offset 0x4 per table 2-3 followed, by the DDR controller registers.

    2. Boot table section at 400 MHz

    Ricardo Martinez said:
    00 00 00 70 00 8F 35 00 02 42 80 F5 00 00 00 00 00 00 00 0C 00 00 00 02
    63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

    Now please see the SDRAM config and SDTIM registers following the PLL config highlighted in green. You said you are updating the timing parameters to go with the new frequency, but I see they are exactly the same. The green highlighted values should change. Perhaps this is the reason it does not work at 400 MHz without leveling?

  • 0 in reply to Aditya
    Intellectual 290 points

    Answering your first reply, yes, everything works OK at 666.67MHz (which means DDR3-1333).

    With respect to your second reply

    1) Table 2-3 in bootloader user guide is wrong. It has been reported in a few posts but Texas has not yet delivered a corrected version of this document. You can check the correct table format in tiboot_c66x.h file in C:\ti\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\device\c66x,

    typedef struct bootEmif4Tbl_s  

     As I said, this errata has already been reported.

    2) This has been a copy-paste error, sorry. Updated values for 400MHz (DDR3-800) are:

    00 00 00 70 00 8F 35 00 02 42 80 F5 00 00 00 00 00 00 00 0C 00 00 00 02
    63 06 2A 32 00 00 00 00 00 00 0C 30 0C CF 36 A3 30 30 FF D2 55 FF 83 AF
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

    Please note that values above do work using GEL/Emulator. So the problem is not related to timing parameters (I think).

    Quoting your last sentence: "Perhaps this is the reason it does not work at 400 MHz without leveling?"

    Please not that this is not the root of the problem I am stating in this post.

    This post is about not being possible to configure leveling from ROM Bootloader. If it is not possible to configure leveling, I might think that loading application into DDR3 might not be as reliable as desirable. So I was thinking that lowering down DDR3 CLK to 400MHz might be a solution for the lack of leveling configuration in ROM Bootloader.

    Two different problems:

    1) ROM Bootloader does not seem to configure leveling. So I think that application might NOT be loaded into DDR3 reliably at DDR3-1333

    2) ROM Bootloader does not load application into DDR3 when ROM Bootloader configures DDR3 CLK at any value below 666.67MHz. Concrete example above is trying to configure DDR3 CLK at 400MHz (DDR3-800). This example works OK when loading platform with Emulator (GEL file with updated DDR3 configuration parameters).

     

     

  • 0 in reply to Ricardo Martinez
    TI__Expert 6815 points

    1) Okay, good. Let me check internally where we are on that.

    2) After you configure DDR3-1333 and load your application code - and before you perform any CPU/non-CPU initiated traffic to DDR - please dump your DDR PLLCTL0/1 registers and DDR config space from 0x21000000 -> 0x21000100. As part of this debug, I want to take a look at why is it that you do not face an issue at this freq w/o leveling and also sanity check the config space values.

    I understand what your problem is. Please understand that these are debug steps that are necessary to eliminate variables and focus on what really is going on.

    3) Would it be possible for you to do the same as #2 with DDR-800 that does not work? Perhaps load your code in MSMC or L2 instead of DDR.

  • 0 in reply to Aditya
    Intellectual 290 points

    Thanks for your reply.

    2) I'm pasting the content of the registers after Ethernet load with DDR3-1333 configuration. First column is address and the second the value. Highlighted in blue is DDR3PLLCTL0. The following are DDR3PLLCTL1, PASSPLLCTL* and and SGMII_SERDES_CFG* registers.

    DDR3 configuration registers from 0x21000000 to 0x21000100 as you requested:

     

     

    3) Registers for DDR3-800 configuration:

     

    The first weird behaviour that can be seen it is for both configurations (even for DDR3-1333 for which everything works OK), 0x21000004 register (DDR3 controller status register) bit IFRDY is not stable (in captures above its value is '0', which is really bad, but if I step a few cycles, it becomes '1', and '0' again after a few cycles, and so on). In other words, IFRDY bit is blinking, which is not desirable at all.

    When configuring this from GEL/Emulator, that IFRDY bit is stable as expected (and of course at '1'). Last byte of DDR3 controller status register must be 0x4.

    But it is blinking from 0x4 to 0x0 when RBL Ethernet loading.

     

    Thanks in advance.

     

    Regards 

    Ricardo

  • 0 in reply to Ricardo Martinez
    Intellectual 290 points

    Hi,

    I would like to know if there are any news here.

    Thank you.

    Regards,

    Ricardo

  • 0 in reply to Ricardo Martinez
    Intellectual 290 points

    Still waiting for any feedback...

  • 0 in reply to Ricardo Martinez
    TI__Guru** 116170 points

    Have tried using 2 stage boot instead of using the DDR3 configuration table as discussed on the e2e thread here:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/243149/871674.aspx

    In this case you can boot a small secondary boot loader running from L2 memory or MSMC that performs the leveling and reenters boot. This should help you overcome the leveling issue. We provide the C6670 ROM source with the map file for the ROM on the following wiki:

    http://processors.wiki.ti.com/index.php/Keystone_Device_Architecture (Keystone ROM  examples section)

    Shannon.map file in the ROM source will given the ROM boot re-entry address(_romtBootReentry).

    Regards,

    Rahul